<AVRPART><MODULE_LIST>[CORE:INTERRUPT_VECTOR:PACKAGE:POWER:PROGVOLT:LOCKBIT:FUSE:ADMIN:MEMORY:IO_MODULE:ICE_SETTINGS]</MODULE_LIST><CORE>
<CORE_VERSION>V2</CORE_VERSION>
<ID>AVRSimCoreV2.SimCoreV2</ID>
<NEW_INSTRUCTIONS>[]</NEW_INSTRUCTIONS>
<INSTRUCTIONS_NOT_SUPPORTED>[movw:break:lpm rd,z:spm]</INSTRUCTIONS_NOT_SUPPORTED>
<RAMP_REGISTERS>[]</RAMP_REGISTERS>
<GP_REG_FILE>
<NMB_REG>32</NMB_REG>
<START_ADDR>$00</START_ADDR>
<X_REG_HIGH>$1B</X_REG_HIGH>
<X_REG_LOW>$1A</X_REG_LOW>
<Y_REG_HIGH>$1D</Y_REG_HIGH>
<Y_REG_LOW>$1C</Y_REG_LOW>
<Z_REG_HIGH>$1F</Z_REG_HIGH>
<Z_REG_LOW>$1E</Z_REG_LOW>
</GP_REG_FILE>
</CORE>
<INTERRUPT_VECTOR>
<NMB_VECTORS>21</NMB_VECTORS>
<VECTOR1>
<PROGRAM_ADDRESS>$000</PROGRAM_ADDRESS>
<SOURCE>RESET</SOURCE>
<DEFINITION>External Reset, Power-on Reset and Watchdog Reset</DEFINITION>
</VECTOR1>
<VECTOR2>
<PROGRAM_ADDRESS>$002</PROGRAM_ADDRESS>
<SOURCE>INT0</SOURCE>
<DEFINITION>External Interrupt 0</DEFINITION>
</VECTOR2>
<VECTOR3>
<PROGRAM_ADDRESS>$004</PROGRAM_ADDRESS>
<SOURCE>INT1</SOURCE>
<DEFINITION>External Interrupt 1</DEFINITION>
</VECTOR3>
<VECTOR4>
<PROGRAM_ADDRESS>$006</PROGRAM_ADDRESS>
<SOURCE>INT2</SOURCE>
<DEFINITION>External Interrupt 2</DEFINITION>
</VECTOR4>
<VECTOR5>
<PROGRAM_ADDRESS>$008</PROGRAM_ADDRESS>
<SOURCE>TIMER2_COMP</SOURCE>
<DEFINITION>Timer/Counter2 Compare Match</DEFINITION>
</VECTOR5>
<VECTOR6>
<PROGRAM_ADDRESS>$00A</PROGRAM_ADDRESS>
<SOURCE>TIMER2_OVF</SOURCE>
<DEFINITION>Timer/Counter2 Overflow</DEFINITION>
</VECTOR6>
<VECTOR7>
<PROGRAM_ADDRESS>$00C</PROGRAM_ADDRESS>
<SOURCE>TIMER1_CAPT</SOURCE>
<DEFINITION>Timer/Counter1 Capture Event</DEFINITION>
</VECTOR7>
<VECTOR8>
<PROGRAM_ADDRESS>$00E</PROGRAM_ADDRESS>
<SOURCE>TIMER1_COMPA</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match A</DEFINITION>
</VECTOR8>
<VECTOR9>
<PROGRAM_ADDRESS>$010</PROGRAM_ADDRESS>
<SOURCE>TIMER1_COMPB</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match B</DEFINITION>
</VECTOR9>
<VECTOR10>
<PROGRAM_ADDRESS>$012</PROGRAM_ADDRESS>
<SOURCE>TIMER1_OVF</SOURCE>
<DEFINITION>Timer/Counter1 Overflow</DEFINITION>
</VECTOR10>
<VECTOR11>
<PROGRAM_ADDRESS>$014</PROGRAM_ADDRESS>
<SOURCE>TIMER0_COMP</SOURCE>
<DEFINITION>Timer/Counter0 Compare Match</DEFINITION>
</VECTOR11>
<VECTOR12>
<PROGRAM_ADDRESS>$016</PROGRAM_ADDRESS>
<SOURCE>TIMER0_OVF</SOURCE>
<DEFINITION>Timer/Counter0 Overflow</DEFINITION>
</VECTOR12>
<VECTOR13>
<PROGRAM_ADDRESS>$018</PROGRAM_ADDRESS>
<SOURCE>SPI,STC</SOURCE>
<DEFINITION>Serial Transfer Complete</DEFINITION>
</VECTOR13>
<VECTOR14>
<PROGRAM_ADDRESS>$01A</PROGRAM_ADDRESS>
<SOURCE>UART0,RX</SOURCE>
<DEFINITION>UART0, Rx Complete</DEFINITION>
</VECTOR14>
<VECTOR15>
<PROGRAM_ADDRESS>$01C</PROGRAM_ADDRESS>
<SOURCE>UART1,RX</SOURCE>
<DEFINITION>UART1, Rx Complete</DEFINITION>
</VECTOR15>
<VECTOR16>
<PROGRAM_ADDRESS>$01E</PROGRAM_ADDRESS>
<SOURCE>UART0,UDRE</SOURCE>
<DEFINITION>UART0 Data Register Empty</DEFINITION>
</VECTOR16>
<VECTOR17>
<PROGRAM_ADDRESS>$020</PROGRAM_ADDRESS>
<SOURCE>UART1,UDRE</SOURCE>
<DEFINITION>UART1 Data Register Empty</DEFINITION>
</VECTOR17>
<VECTOR18>
<PROGRAM_ADDRESS>$022</PROGRAM_ADDRESS>
<SOURCE>UART0,TX</SOURCE>
<DEFINITION>UART0, Tx Complete</DEFINITION>
</VECTOR18>
<VECTOR19>
<PROGRAM_ADDRESS>$024</PROGRAM_ADDRESS>
<SOURCE>UART1,TX</SOURCE>
<DEFINITION>UART1, Tx Complete</DEFINITION>
</VECTOR19>
<VECTOR20>
<PROGRAM_ADDRESS>$026</PROGRAM_ADDRESS>
<SOURCE>EE_RDY</SOURCE>
<DEFINITION>EEPROM Ready</DEFINITION>
</VECTOR20>
<VECTOR21>
<PROGRAM_ADDRESS>$028</PROGRAM_ADDRESS>
<SOURCE>ANA_COMP</SOURCE>
<DEFINITION>Analog Comparator</DEFINITION>
</VECTOR21>
</INTERRUPT_VECTOR>
<PACKAGE>
<PACKAGES>[TQFP]</PACKAGES>
<TQFP>
<NMB_PIN>44</NMB_PIN>
<PIN1>
<NAME>[PB5:MOSI]</NAME>
<TEXT>MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details.</TEXT>
</PIN1>
<PIN2>
<NAME>[PB6:MISO]</NAME>
<TEXT>MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further details.</TEXT>
</PIN2>
<PIN3>
<NAME>[PB7:SCK]</NAME>
<TEXT>SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further details.</TEXT>
</PIN3>
<PIN4>
<NAME>['RESET]</NAME>
<TEXT/>
</PIN4>
<PIN5>
<NAME>[PD0:RXD]</NAME>
<TEXT>Receive Data (data input pin for the UART). When the UART receiver is enabled, this pin is configured as an input, regardless of the value of DDRD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.</TEXT>
</PIN5>
<PIN6>
<NAME>[NC]</NAME>
<TEXT/>
</PIN6>
<PIN7>
<NAME>[PD1:TXD]</NAME>
<TEXT>Transmit Data (data output pin for the UART). When the UART transmitter is enabled, this pin is configured as an output, regardless of the value of DDRD1.</TEXT>
</PIN7>
<PIN8>
<NAME>[PD2:INT0]</NAME>
<TEXT>INT0: External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</TEXT>
</PIN8>
<PIN9>
<NAME>[PD3:INT1]</NAME>
<TEXT>INT1: External Interrupt source 1. The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</TEXT>
</PIN9>
<PIN10>
<NAME>[PD4]</NAME>
<TEXT/>
</PIN10>
<PIN11>
<NAME>[PD5:OC1A:TOSC2]</NAME>
<TEXT>OC1A: Output compare match output. The PD5 pin can serve as an external output when the Timer/Counter1 compare matches. The PD5 pin has to be configured as an output (DDD5 set [one]) to serve this function. See the Timer/Counter1 description for further details and how to enable the output. The OC1A pin is also the output pin for the PWM mode timer function.</TEXT>
</PIN11>
<PIN12>
<NAME>[PD6:'WR]</NAME>
<TEXT>WR is the external data memory write control strobe. See “Interface to External SRAM” on page 52 for detailed information.</TEXT>
</PIN12>
<PIN13>
<NAME>[PD7:'RD]</NAME>
<TEXT>RD is the external data memory read control strobe. See “Interface to External SRAM” on page 52 for detailed information.</TEXT>
</PIN13>
<PIN14>
<NAME>[XTAL2]</NAME>
<TEXT/>
</PIN14>
<PIN15>
<NAME>[XTAL1]</NAME>
<TEXT/>
</PIN15>
<PIN16>
<NAME>[GND]</NAME>
<TEXT/>
</PIN16>
<PIN17>
<NAME>[NC]</NAME>
<TEXT/>
</PIN17>
<PIN18>
<NAME>[PC0:A8]</NAME>
<TEXT/>
</PIN18>
<PIN19>
<NAME>[PC1:A9]</NAME>
<TEXT/>
</PIN19>
<PIN20>
<NAME>[PC2:A10]</NAME>
<TEXT/>
</PIN20>
<PIN21>
<NAME>[PC3:A11]</NAME>
<TEXT/>
</PIN21>
<PIN22>
<NAME>[PC4:A12]</NAME>
<TEXT/>
</PIN22>
<PIN23>
<NAME>[PC5:A13]</NAME>
<TEXT/>
</PIN23>
<PIN24>
<NAME>[PC6:A14]</NAME>
<TEXT/>
</PIN24>
<PIN25>
<NAME>[PC7:A15]</NAME>
<TEXT/>
</PIN25>
<PIN26>
<NAME>[PE2:OC1B]</NAME>
<TEXT/>
</PIN26>
<PIN27>
<NAME>[PE1:ALE]</NAME>
<TEXT/>
</PIN27>
<PIN28>
<NAME>[NC]</NAME>
<TEXT/>
</PIN28>
<PIN29>
<NAME>[PE0:ICP/INT2]</NAME>
<TEXT/>
</PIN29>
<PIN30>
<NAME>[PA7:AD7]</NAME>
<TEXT/>
</PIN30>
<PIN31>
<NAME>[PA6:AD6]</NAME>
<TEXT/>
</PIN31>
<PIN32>
<NAME>[PA5:AD5]</NAME>
<TEXT/>
</PIN32>
<PIN33>
<NAME>[PA4:AD4]</NAME>
<TEXT/>
</PIN33>
<PIN34>
<NAME>[PA3:AD3]</NAME>
<TEXT/>
</PIN34>
<PIN35>
<NAME>[PA2:AD2]</NAME>
<TEXT/>
</PIN35>
<PIN36>
<NAME>[PA1:AD1]</NAME>
<TEXT/>
</PIN36>
<PIN37>
<NAME>[PA0:AD0]</NAME>
<TEXT/>
</PIN37>
<PIN38>
<NAME>[VCC]</NAME>
<TEXT/>
</PIN38>
<PIN39>
<NAME>[NC]</NAME>
<TEXT/>
</PIN39>
<PIN40>
<NAME>[PB0:OC0/T0]</NAME>
<TEXT>T0: Timer/Counter0 counter source. See the timer description for further details.</TEXT>
</PIN40>
<PIN41>
<NAME>[PB1:OC2/T1]</NAME>
<TEXT>T1: Timer/Counter1 counter source. See the timer description for further details</TEXT>
</PIN41>
<PIN42>
<NAME>[PB2:RXD1:AIN0]</NAME>
<TEXT>AIN0: Analog Comparator Positive Input. When configured as an input (DDB2 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]), this pin also serves as the positive input of the on-chip Analog Comparator.</TEXT>
</PIN42>
<PIN43>
<NAME>[PB3:TXD1:AIN1]</NAME>
<TEXT>AIN1: Analog Comparator Negative Input. When configured as an input (DDB3 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared [zero]), this pin also serves as the negative input of the on-chip Analog Comparator.</TEXT>
</PIN43>
<PIN44>
<NAME>[PB4:SS]</NAME>
<TEXT>SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details.</TEXT>
</PIN44>
</TQFP>
</PACKAGE>
<POWER>
<CLOCK>4MHz</CLOCK>
<TEMP>25C</TEMP>
<ACTIVE>3.0 mA</ACTIVE>
<IDLE>1.2 mA</IDLE>
<POWER_DOWN><1uA</POWER_DOWN>
</POWER>
<PROGVOLT>
<SER_PROG_MIN_V>4.0</SER_PROG_MIN_V>
<SER_PROG_MAX_V>5.5</SER_PROG_MAX_V>
<PAR_PROG_MIN_V>4.0</PAR_PROG_MIN_V>
<PAR_PROG_MAX_V>5.5</PAR_PROG_MAX_V>
</PROGVOLT>
<LOCKBIT>
<ICON/>
<ID/>
<TEXT>[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled</TEXT>
<NMB_LOCK_BITS>6</NMB_LOCK_BITS>
<NMB_TEXT>11</NMB_TEXT>
<TEXT1>
<MASK>0x03</MASK>
<VALUE>0x03</VALUE>
<TEXT>Mode 1: No memory lock features enabled</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x03</MASK>
<VALUE>0x02</VALUE>
<TEXT>Mode 2: Further programming disabled</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x03</MASK>
<VALUE>0x00</VALUE>
<TEXT>Mode 3: Further programming and verification disabled</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x0C</MASK>
<VALUE>0x0C</VALUE>
<TEXT>Application Protection Mode 1: No lock on SPM and LPM in Application Section</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x0C</MASK>
<VALUE>0x08</VALUE>
<TEXT>Application Protection Mode 2: SPM prohibited in Application Section</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x0C</MASK>
<VALUE>0x00</VALUE>
<TEXT>Application Protection Mode 3: LPM and SPM prohibited in Application Section</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x0C</MASK>
<VALUE>0x04</VALUE>
<TEXT>Application Protection Mode 4: LPM prohibited in Application Section</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x30</MASK>
<VALUE>0x30</VALUE>
<TEXT>Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x30</MASK>
<VALUE>0x20</VALUE>
<TEXT>Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x30</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x30</MASK>
<VALUE>0x10</VALUE>
<TEXT>Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section</TEXT>
</TEXT11>
<LOCKBIT0>
<NAME>LB1</NAME>
<TEXT>Lock bit</TEXT>
</LOCKBIT0>
<LOCKBIT1>
<NAME>LB2</NAME>
<TEXT>Lock bit</TEXT>
</LOCKBIT1>
<LOCKBIT2>
<NAME>BLB01</NAME>
<TEXT>Boot Lock bit</TEXT>
</LOCKBIT2>
<LOCKBIT3>
<NAME>BLB02</NAME>
<TEXT>Boot Lock bit</TEXT>
</LOCKBIT3>
<LOCKBIT4>
<NAME>BLB11</NAME>
<TEXT>Boot lock bit</TEXT>
</LOCKBIT4>
<LOCKBIT5>
<NAME>BLB12</NAME>
<TEXT>Boot lock bit</TEXT>
</LOCKBIT5>
</LOCKBIT>
<FUSE>
<LIST>[LOW:HIGH:EXTENDED]</LIST>
<ID/>
<ICON/>
<TEXT/>
<LOW>
<NMB_FUSE_BITS>8</NMB_FUSE_BITS>
<FUSE7>
<NAME>CLKDIV8</NAME>
<TEXT>Divide clock by 8</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE7>
<FUSE6>
<NAME>CKOUT</NAME>
<TEXT>Oscillator options</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE6>
<FUSE5>
<NAME>SUT1</NAME>
<TEXT>Select start-up time</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE5>
<FUSE4>
<NAME>SUT0</NAME>
<TEXT>Select start-up time</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE4>
<FUSE3>
<NAME>CKSEL3</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE3>
<FUSE2>
<NAME>CKSEL2</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>CKSEL1</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>CKSEL0</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<NMB_TEXT>52</NMB_TEXT>
<TEXT1>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>Divide clock by 8 internally; [CKDIV8=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x40</MASK>
<VALUE>0x00</VALUE>
<TEXT>Clock output on PORTB0; [CKOUT=0]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x3F</MASK>
<VALUE>0x00</VALUE>
<TEXT>Ext. Clock; Start-up time: 6 CK + 0 ms; [CKSEL=0000 SUT=00]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x3F</MASK>
<VALUE>0x10</VALUE>
<TEXT>Ext. Clock; Start-up time: 6 CK + 4.1 ms; [CKSEL=0000 SUT=01]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x3F</MASK>
<VALUE>0x20</VALUE>
<TEXT>Ext. Clock; Start-up time: 6 CK + 65 ms; [CKSEL=0000 SUT=10]</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x3F</MASK>
<VALUE>0x02</VALUE>
<TEXT>Int. RC Osc.; Start-up time: 6 CK + 0 ms; [CKSEL=0010 SUT=00]</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x3F</MASK>
<VALUE>0x12</VALUE>
<TEXT>Int. RC Osc.; Start-up time: 6 CK + 4.1 ms; [CKSEL=0010 SUT=01]</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x3F</MASK>
<VALUE>0x22</VALUE>
<TEXT>Int. RC Osc.; Start-up time: 6 CK + 65 ms; [CKSEL=0010 SUT=10]</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x3F</MASK>
<VALUE>0x07</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms; Int. Cap.; [CKSEL=0111 SUT=00]</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x3F</MASK>
<VALUE>0x17</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms; Int. Cap.; [CKSEL=0111 SUT=01]</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x3F</MASK>
<VALUE>0x27</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms; Int. Cap.; [CKSEL=0111 SUT=10]</TEXT>
</TEXT11>
<TEXT12>
<MASK>0x3F</MASK>
<VALUE>0x06</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms; Int. Cap.; [CKSEL=0110 SUT=00]</TEXT>
</TEXT12>
<TEXT13>
<MASK>0x3F</MASK>
<VALUE>0x16</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms; Int. Cap.; [CKSEL=0110 SUT=01]</TEXT>
</TEXT13>
<TEXT14>
<MASK>0x3F</MASK>
<VALUE>0x26</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms; Int. Cap.; [CKSEL=0110 SUT=10]</TEXT>
</TEXT14>
<TEXT15>
<MASK>0x3F</MASK>
<VALUE>0x05</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms; [CKSEL=0101 SUT=00]</TEXT>
</TEXT15>
<TEXT16>
<MASK>0x3F</MASK>
<VALUE>0x15</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms; [CKSEL=0101 SUT=01]</TEXT>
</TEXT16>
<TEXT17>
<MASK>0x3F</MASK>
<VALUE>0x25</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms; [CKSEL=0101 SUT=10]</TEXT>
</TEXT17>
<TEXT18>
<MASK>0x3F</MASK>
<VALUE>0x04</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms; [CKSEL=0100 SUT=00]</TEXT>
</TEXT18>
<TEXT19>
<MASK>0x3F</MASK>
<VALUE>0x14</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms; [CKSEL=0100 SUT=01]</TEXT>
</TEXT19>
<TEXT20>
<MASK>0x3F</MASK>
<VALUE>0x24</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms; [CKSEL=0100 SUT=10]</TEXT>
</TEXT20>
<TEXT21>
<MASK>0x3F</MASK>
<VALUE>0x08</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1000 SUT=00]</TEXT>
</TEXT21>
<TEXT22>
<MASK>0x3F</MASK>
<VALUE>0x18</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1000 SUT=01]</TEXT>
</TEXT22>
<TEXT23>
<MASK>0x3F</MASK>
<VALUE>0x28</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1000 SUT=10]</TEXT>
</TEXT23>
<TEXT24>
<MASK>0x3F</MASK>
<VALUE>0x38</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1000 SUT=11]</TEXT>
</TEXT24>
<TEXT25>
<MASK>0x3F</MASK>
<VALUE>0x09</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1001 SUT=00]</TEXT>
</TEXT25>
<TEXT26>
<MASK>0x3F</MASK>
<VALUE>0x19</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1001 SUT=01]</TEXT>
</TEXT26>
<TEXT27>
<MASK>0x3F</MASK>
<VALUE>0x29</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1001 SUT=10]</TEXT>
</TEXT27>
<TEXT28>
<MASK>0x3F</MASK>
<VALUE>0x39</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1001 SUT=11]</TEXT>
</TEXT28>
<TEXT29>
<MASK>0x3F</MASK>
<VALUE>0x0A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1010 SUT=00]</TEXT>
</TEXT29>
<TEXT30>
<MASK>0x3F</MASK>
<VALUE>0x1A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1010 SUT=01]</TEXT>
</TEXT30>
<TEXT31>
<MASK>0x3F</MASK>
<VALUE>0x2A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1010 SUT=10]</TEXT>
</TEXT31>
<TEXT32>
<MASK>0x3F</MASK>
<VALUE>0x3A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1010 SUT=11]</TEXT>
</TEXT32>
<TEXT33>
<MASK>0x3F</MASK>
<VALUE>0x0B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1011 SUT=00]</TEXT>
</TEXT33>
<TEXT34>
<MASK>0x3F</MASK>
<VALUE>0x1B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1011 SUT=01]</TEXT>
</TEXT34>
<TEXT35>
<MASK>0x3F</MASK>
<VALUE>0x2B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1011 SUT=10]</TEXT>
</TEXT35>
<TEXT36>
<MASK>0x3F</MASK>
<VALUE>0x3B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1011 SUT=11]</TEXT>
</TEXT36>
<TEXT37>
<MASK>0x3F</MASK>
<VALUE>0x0C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1100 SUT=00]</TEXT>
</TEXT37>
<TEXT38>
<MASK>0x3F</MASK>
<VALUE>0x1C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1100 SUT=01]</TEXT>
</TEXT38>
<TEXT39>
<MASK>0x3F</MASK>
<VALUE>0x2C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1100 SUT=10]</TEXT>
</TEXT39>
<TEXT40>
<MASK>0x3F</MASK>
<VALUE>0x3C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1100 SUT=11]</TEXT>
</TEXT40>
<TEXT41>
<MASK>0x3F</MASK>
<VALUE>0x0D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1101 SUT=00]</TEXT>
</TEXT41>
<TEXT42>
<MASK>0x3F</MASK>
<VALUE>0x1D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1101 SUT=01]</TEXT>
</TEXT42>
<TEXT43>
<MASK>0x3F</MASK>
<VALUE>0x2D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1101 SUT=10]</TEXT>
</TEXT43>
<TEXT44>
<MASK>0x3F</MASK>
<VALUE>0x3D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1101 SUT=11]</TEXT>
</TEXT44>
<TEXT45>
<MASK>0x3F</MASK>
<VALUE>0x0E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1110 SUT=00]</TEXT>
</TEXT45>
<TEXT46>
<MASK>0x3F</MASK>
<VALUE>0x1E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1110 SUT=01]</TEXT>
</TEXT46>
<TEXT47>
<MASK>0x3F</MASK>
<VALUE>0x2E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1110 SUT=10]</TEXT>
</TEXT47>
<TEXT48>
<MASK>0x3F</MASK>
<VALUE>0x3E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1110 SUT=11]</TEXT>
</TEXT48>
<TEXT49>
<MASK>0x3F</MASK>
<VALUE>0x0F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1111 SUT=00]</TEXT>
</TEXT49>
<TEXT50>
<MASK>0x3F</MASK>
<VALUE>0x1F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1111 SUT=01]</TEXT>
</TEXT50>
<TEXT51>
<MASK>0x3F</MASK>
<VALUE>0x2F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1111 SUT=10]</TEXT>
</TEXT51>
<TEXT52>
<MASK>0x3F</MASK>
<VALUE>0x3F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1111 SUT=11]</TEXT>
</TEXT52>
</LOW>
<HIGH>
<NMB_FUSE_BITS>8</NMB_FUSE_BITS>
<FUSE7>
<NAME>OCDEN</NAME>
<TEXT>Enable OCD</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE7>
<FUSE6>
<NAME>JTAGEN</NAME>
<TEXT>Enable JTAG</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE6>
<FUSE5>
<NAME>SPIEN</NAME>
<TEXT>Enable Serial programming and Data Downloading</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE5>
<FUSE4>
<NAME>WDTON</NAME>
<TEXT>Watchdog timer always on</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE4>
<FUSE3>
<NAME>EESAVE</NAME>
<TEXT>EEPROM memory is preserved through chip erase</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE3>
<FUSE2>
<NAME>BOOTSZ1</NAME>
<TEXT>Select Boot Size</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>BOOTSZ0</NAME>
<TEXT>Select Boot Size</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>BOOTRST</NAME>
<TEXT>Select Reset Vector</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<NMB_TEXT>10</NMB_TEXT>
<TEXT1>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>On-Chip Debug Enabled; [OCDEN=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x40</MASK>
<VALUE>0x00</VALUE>
<TEXT>JTAG Interface Enabled; [JTAGEN=0]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x20</MASK>
<VALUE>0x00</VALUE>
<TEXT>Serial program downloading (SPI) enabled; [SPIEN=0]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x10</MASK>
<VALUE>0x00</VALUE>
<TEXT>Watchdog timer always on; [WDTON=0]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x08</MASK>
<VALUE>0x00</VALUE>
<TEXT>Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x06</MASK>
<VALUE>0x06</VALUE>
<TEXT>Boot Flash section size=128 words Boot start address=$1F80; [BOOTSZ=11]</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x06</MASK>
<VALUE>0x04</VALUE>
<TEXT>Boot Flash section size=256 words Boot start address=$1F00; [BOOTSZ=10]</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x06</MASK>
<VALUE>0x02</VALUE>
<TEXT>Boot Flash section size=512 words Boot start address=$1E00; [BOOTSZ=01]</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x06</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Flash section size=1024 words Boot start address=$1C00; [BOOTSZ=00] ; default value</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x01</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]</TEXT>
</TEXT10>
</HIGH>
<EXTENDED>
<NMB_FUSE_BITS>4</NMB_FUSE_BITS>
<FUSE4>
<NAME>M161C</NAME>
<TEXT>ATMega 161 compatibility mode</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE4>
<FUSE3>
<NAME>BODLEVEL2</NAME>
<TEXT>Brown out detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE3>
<FUSE2>
<NAME>BODLEVEL1</NAME>
<TEXT>Brown out detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>BODLEVEL0</NAME>
<TEXT>Brown out detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE1>
<NMB_TEXT>5</NMB_TEXT>
<TEXT1>
<MASK>0x10</MASK>
<VALUE>0x00</VALUE>
<TEXT>ATmega161 compability mode; [M161C=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x0E</MASK>
<VALUE>0x0E</VALUE>
<TEXT>Brown-out detection disabled; [BODLEVEL=111]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x0E</MASK>
<VALUE>0x0C</VALUE>
<TEXT>Brown-out detection level at VCC=1.8 V; [BODLEVEL=110]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x0E</MASK>
<VALUE>0x0A</VALUE>
<TEXT>Brown-out detection level at VCC=2.7 V; [BODLEVEL=101]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x0E</MASK>
<VALUE>0x08</VALUE>
<TEXT>Brown-out detection level at VCC=4.3 V; [BODLEVEL=100]</TEXT>
</TEXT5>
</EXTENDED>
</FUSE>
<ADMIN>
<PART_NAME>ATmega161comp</PART_NAME>
<SPEED>8MHZ</SPEED>
<BUILD>1</BUILD>
<RELEASE_STATUS>RELEASED</RELEASE_STATUS>
<NO_INCLUDE_FILE>Y</NO_INCLUDE_FILE>
<SIGNATURE>
<ADDR000>$1E</ADDR000>
<ADDR001>$94</ADDR001>
<ADDR002>$01</ADDR002>
</SIGNATURE>
<COMPATIBILITYMODE>
<COMPATIBILITYPART>ATmega161comp</COMPATIBILITYPART>
<NORMAL>ATmega162</NORMAL>
</COMPATIBILITYMODE>
</ADMIN>
<MEMORY>
<ID>AVRSimMemory8bit.SimMemory8bit</ID>
<PROG_FLASH>16384</PROG_FLASH>
<EEPROM>512</EEPROM>
<INT_SRAM>
<SIZE>1024</SIZE>
<START_ADDR>$60</START_ADDR>
</INT_SRAM>
<EXT_SRAM>
<SIZE>65536</SIZE>
<START_ADDR>$460</START_ADDR>
</EXT_SRAM>
<IO_MEMORY>
<IO_START_ADDR>$00</IO_START_ADDR>
<IO_STOP_ADDR>$3F</IO_STOP_ADDR>
<EXT_IO_START_ADDR>NA</EXT_IO_START_ADDR>
<EXT_IO_STOP_ADDR>NA</EXT_IO_STOP_ADDR>
<MEM_START_ADDR>$20</MEM_START_ADDR>
<MEM_STOP_ADDR>$5f</MEM_STOP_ADDR>
<TCCR3A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8B</MEM_ADDR>
</TCCR3A>
<TCCR3B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8A</MEM_ADDR>
</TCCR3B>
<TCNT3H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$89</MEM_ADDR>
</TCNT3H>
<TCNT3L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$88</MEM_ADDR>
</TCNT3L>
<OCR3AH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$87</MEM_ADDR>
</OCR3AH>
<OCR3AL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$86</MEM_ADDR>
</OCR3AL>
<OCR3BH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$85</MEM_ADDR>
</OCR3BH>
<OCR3BL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$84</MEM_ADDR>
</OCR3BL>
<ICR3H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$81</MEM_ADDR>
</ICR3H>
<ICR3L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$80</MEM_ADDR>
</ICR3L>
<ETIMSK>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7D</MEM_ADDR>
</ETIMSK>
<ETIFR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7C</MEM_ADDR>
</ETIFR>
<PCMSK1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6C</MEM_ADDR>
<PCINT8_MASK>0x01</PCINT8_MASK><PCINT9_MASK>0x02</PCINT9_MASK><PCINT10_MASK>0x04</PCINT10_MASK><PCINT11_MASK>0x08</PCINT11_MASK><PCINT12_MASK>0x10</PCINT12_MASK><PCINT13_MASK>0x20</PCINT13_MASK><PCINT14_MASK>0x40</PCINT14_MASK><PCINT15_MASK>0x80</PCINT15_MASK></PCMSK1>
<PCMSK0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6B</MEM_ADDR>
<PCINT0_MASK>0x01</PCINT0_MASK><PCINT1_MASK>0x02</PCINT1_MASK><PCINT2_MASK>0x04</PCINT2_MASK><PCINT3_MASK>0x08</PCINT3_MASK><PCINT4_MASK>0x10</PCINT4_MASK><PCINT5_MASK>0x20</PCINT5_MASK><PCINT6_MASK>0x40</PCINT6_MASK><PCINT7_MASK>0x80</PCINT7_MASK></PCMSK0>
<CLKPR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$61</MEM_ADDR>
<CLKPS0_MASK>0x01</CLKPS0_MASK><CLKPS1_MASK>0x02</CLKPS1_MASK><CLKPS2_MASK>0x04</CLKPS2_MASK><CLKPS3_MASK>0x08</CLKPS3_MASK><CLKPCE_MASK>0x80</CLKPCE_MASK></CLKPR>
<SREG>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<C_MASK>0x01</C_MASK><Z_MASK>0x02</Z_MASK><N_MASK>0x04</N_MASK><V_MASK>0x08</V_MASK><S_MASK>0x10</S_MASK><H_MASK>0x20</H_MASK><T_MASK>0x40</T_MASK><I_MASK>0x80</I_MASK></SREG>
<SPH>
<IO_ADDR>$3E</IO_ADDR>
<MEM_ADDR>$5E</MEM_ADDR>
<SP8_MASK>0x01</SP8_MASK><SP9_MASK>0x02</SP9_MASK><SP10_MASK>0x04</SP10_MASK><SP11_MASK>0x08</SP11_MASK><SP12_MASK>0x10</SP12_MASK><SP13_MASK>0x20</SP13_MASK><SP14_MASK>0x40</SP14_MASK><SP15_MASK>0x80</SP15_MASK></SPH>
<SPL>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<SP0_MASK>0x01</SP0_MASK><SP1_MASK>0x02</SP1_MASK><SP2_MASK>0x04</SP2_MASK><SP3_MASK>0x08</SP3_MASK><SP4_MASK>0x10</SP4_MASK><SP5_MASK>0x20</SP5_MASK><SP6_MASK>0x40</SP6_MASK><SP7_MASK>0x80</SP7_MASK></SPL>
<UBRR1H>
<IO_ADDR>$3C</IO_ADDR>
<MEM_ADDR>$5C</MEM_ADDR>
<UBRR8_MASK>0x01</UBRR8_MASK><UBRR9_MASK>0x02</UBRR9_MASK><UBRR10_MASK>0x04</UBRR10_MASK><UBRR11_MASK>0x08</UBRR11_MASK></UBRR1H>
<UCSR1C>
<IO_ADDR>$3C</IO_ADDR>
<MEM_ADDR>$5C</MEM_ADDR>
<UCPOL1_MASK>0x01</UCPOL1_MASK><UCSZ10_MASK>0x02</UCSZ10_MASK><UCSZ11_MASK>0x04</UCSZ11_MASK><USBS1_MASK>0x08</USBS1_MASK><UPM10_MASK>0x10</UPM10_MASK><UPM11_MASK>0x20</UPM11_MASK><UMSEL1_MASK>0x40</UMSEL1_MASK><URSEL1_MASK>0x80</URSEL1_MASK></UCSR1C>
<GICR>
<IO_ADDR>$3B</IO_ADDR>
<MEM_ADDR>$5B</MEM_ADDR>
<IVCE_MASK>0x01</IVCE_MASK><IVSEL_MASK>0x02</IVSEL_MASK><PCIE0_MASK>0x08</PCIE0_MASK><PCIE1_MASK>0x10</PCIE1_MASK><INT2_MASK>0x20</INT2_MASK><INT0_MASK>0x40</INT0_MASK><INT1_MASK>0x80</INT1_MASK></GICR>
<GIFR>
<IO_ADDR>$3A</IO_ADDR>
<MEM_ADDR>$5A</MEM_ADDR>
<PCIF0_MASK>0x08</PCIF0_MASK><PCIF1_MASK>0x10</PCIF1_MASK><INTF2_MASK>0x20</INTF2_MASK><INTF0_MASK>0x40</INTF0_MASK><INTF1_MASK>0x80</INTF1_MASK></GIFR>
<TIMSK>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<OCIE0_MASK>0x01</OCIE0_MASK><TOIE0_MASK>0x02</TOIE0_MASK><TICIE1_MASK>0x08</TICIE1_MASK><OCIE1B_MASK>0x20</OCIE1B_MASK><OCIE1A_MASK>0x40</OCIE1A_MASK><TOIE1_MASK>0x80</TOIE1_MASK><TOIE2_MASK>0x04</TOIE2_MASK><OCIE2_MASK>0x10</OCIE2_MASK></TIMSK>
<TIFR>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<OCF0_MASK>0x01</OCF0_MASK><TOV0_MASK>0x02</TOV0_MASK><ICF1_MASK>0x08</ICF1_MASK><OCF1B_MASK>0x20</OCF1B_MASK><OCF1A_MASK>0x40</OCF1A_MASK><TOV1_MASK>0x80</TOV1_MASK><TOV2_MASK>0x04</TOV2_MASK><OCF2_MASK>0x10</OCF2_MASK></TIFR>
<SPMCR>
<IO_ADDR>$37</IO_ADDR>
<MEM_ADDR>$57</MEM_ADDR>
<SPMEN_MASK>0x01</SPMEN_MASK><PGERS_MASK>0x02</PGERS_MASK><PGWRT_MASK>0x04</PGWRT_MASK><BLBSET_MASK>0x08</BLBSET_MASK><RWWSRE_MASK>0x10</RWWSRE_MASK><RWWSB_MASK>0x40</RWWSB_MASK><SPMIE_MASK>0x80</SPMIE_MASK></SPMCR>
<EMCUCR>
<IO_ADDR>$36</IO_ADDR>
<MEM_ADDR>$56</MEM_ADDR>
<ISC2_MASK>0x01</ISC2_MASK><SRW11_MASK>0x02</SRW11_MASK><SRW00_MASK>0x04</SRW00_MASK><SRW01_MASK>0x08</SRW01_MASK><SRL0_MASK>0x10</SRL0_MASK><SRL1_MASK>0x20</SRL1_MASK><SRL2_MASK>0x40</SRL2_MASK><SM0_MASK>0x80</SM0_MASK></EMCUCR>
<MCUCR>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ISC00_MASK>0x01</ISC00_MASK><ISC01_MASK>0x02</ISC01_MASK><ISC10_MASK>0x04</ISC10_MASK><ISC11_MASK>0x08</ISC11_MASK><SM1_MASK>0x10</SM1_MASK><SE_MASK>0x20</SE_MASK><SRW10_MASK>0x40</SRW10_MASK><SRE_MASK>0x80</SRE_MASK></MCUCR>
<MCUCSR>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<PORF_MASK>0x01</PORF_MASK><EXTRF_MASK>0x02</EXTRF_MASK><BORF_MASK>0x04</BORF_MASK><WDRF_MASK>0x08</WDRF_MASK><JTRF_MASK>0x10</JTRF_MASK><SM2_MASK>0x20</SM2_MASK><JDT_MASK>0x80</JDT_MASK></MCUCSR>
<TCCR0>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<CS00_MASK>0x01</CS00_MASK><CS01_MASK>0x02</CS01_MASK><CS02_MASK>0x04</CS02_MASK><WGM01_MASK>0x08</WGM01_MASK><COM00_MASK>0x10</COM00_MASK><COM01_MASK>0x20</COM01_MASK><WGM00_MASK>0x40</WGM00_MASK><FOC0_MASK>0x80</FOC0_MASK></TCCR0>
<TCNT0>
<IO_ADDR>$32</IO_ADDR>
<MEM_ADDR>$52</MEM_ADDR>
<TCNT0_0_MASK>0x01</TCNT0_0_MASK><TCNT0_1_MASK>0x02</TCNT0_1_MASK><TCNT0_2_MASK>0x04</TCNT0_2_MASK><TCNT0_3_MASK>0x08</TCNT0_3_MASK><TCNT0_4_MASK>0x10</TCNT0_4_MASK><TCNT0_5_MASK>0x20</TCNT0_5_MASK><TCNT0_6_MASK>0x40</TCNT0_6_MASK><TCNT0_7_MASK>0x80</TCNT0_7_MASK></TCNT0>
<OCR0>
<IO_ADDR>$31</IO_ADDR>
<MEM_ADDR>$51</MEM_ADDR>
<OCR0_0_MASK>0x01</OCR0_0_MASK><OCR0_1_MASK>0x02</OCR0_1_MASK><OCR0_2_MASK>0x04</OCR0_2_MASK><OCR0_3_MASK>0x08</OCR0_3_MASK><OCR0_4_MASK>0x10</OCR0_4_MASK><OCR0_5_MASK>0x20</OCR0_5_MASK><OCR0_6_MASK>0x40</OCR0_6_MASK><OCR0_7_MASK>0x80</OCR0_7_MASK></OCR0>
<SFIOR>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
<PSR10_MASK>0x01</PSR10_MASK><PSR310_MASK>0x01</PSR310_MASK><PSR2_MASK>0x02</PSR2_MASK><PUD_MASK>0x04</PUD_MASK><XMM0_MASK>0x08</XMM0_MASK><XMM1_MASK>0x10</XMM1_MASK><XMM2_MASK>0x20</XMM2_MASK><XMBK_MASK>0x40</XMBK_MASK><TSM_MASK>0x80</TSM_MASK></SFIOR>
<TCCR1A>
<IO_ADDR>$2F</IO_ADDR>
<MEM_ADDR>$4F</MEM_ADDR>
<WGM10_MASK>0x01</WGM10_MASK><WGM11_MASK>0x02</WGM11_MASK><FOC1B_MASK>0x04</FOC1B_MASK><FOC1A_MASK>0x08</FOC1A_MASK><COM1B0_MASK>0x10</COM1B0_MASK><COM1B1_MASK>0x20</COM1B1_MASK><COM1A0_MASK>0x40</COM1A0_MASK><COM1A1_MASK>0x80</COM1A1_MASK></TCCR1A>
<TCCR1B>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<CS10_MASK>0x01</CS10_MASK><CS11_MASK>0x02</CS11_MASK><CS12_MASK>0x04</CS12_MASK><CTC1_MASK>0x08</CTC1_MASK><ICES1_MASK>0x40</ICES1_MASK><ICNC1_MASK>0x80</ICNC1_MASK></TCCR1B>
<TCNT1H>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<TCNT1H0_MASK>0x01</TCNT1H0_MASK><TCNT1H1_MASK>0x02</TCNT1H1_MASK><TCNT1H2_MASK>0x04</TCNT1H2_MASK><TCNT1H3_MASK>0x08</TCNT1H3_MASK><TCNT1H4_MASK>0x10</TCNT1H4_MASK><TCNT1H5_MASK>0x20</TCNT1H5_MASK><TCNT1H6_MASK>0x40</TCNT1H6_MASK><TCNT1H7_MASK>0x80</TCNT1H7_MASK></TCNT1H>
<TCNT1L>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<TCNT1L0_MASK>0x01</TCNT1L0_MASK><TCNT1L1_MASK>0x02</TCNT1L1_MASK><TCNT1L2_MASK>0x04</TCNT1L2_MASK><TCNT1L3_MASK>0x08</TCNT1L3_MASK><TCNT1L4_MASK>0x10</TCNT1L4_MASK><TCNT1L5_MASK>0x20</TCNT1L5_MASK><TCNT1L6_MASK>0x40</TCNT1L6_MASK><TCNT1L7_MASK>0x80</TCNT1L7_MASK></TCNT1L>
<OCR1AH>
<IO_ADDR>$2B</IO_ADDR>
<MEM_ADDR>$4B</MEM_ADDR>
<OCR1AH0_MASK>0x01</OCR1AH0_MASK><OCR1AH1_MASK>0x02</OCR1AH1_MASK><OCR1AH2_MASK>0x04</OCR1AH2_MASK><OCR1AH3_MASK>0x08</OCR1AH3_MASK><OCR1AH4_MASK>0x10</OCR1AH4_MASK><OCR1AH5_MASK>0x20</OCR1AH5_MASK><OCR1AH6_MASK>0x40</OCR1AH6_MASK><OCR1AH7_MASK>0x80</OCR1AH7_MASK></OCR1AH>
<OCR1AL>
<IO_ADDR>$2A</IO_ADDR>
<MEM_ADDR>$4A</MEM_ADDR>
<OCR1AL0_MASK>0x01</OCR1AL0_MASK><OCR1AL1_MASK>0x02</OCR1AL1_MASK><OCR1AL2_MASK>0x04</OCR1AL2_MASK><OCR1AL3_MASK>0x08</OCR1AL3_MASK><OCR1AL4_MASK>0x10</OCR1AL4_MASK><OCR1AL5_MASK>0x20</OCR1AL5_MASK><OCR1AL6_MASK>0x40</OCR1AL6_MASK><OCR1AL7_MASK>0x80</OCR1AL7_MASK></OCR1AL>
<OCR1BH>
<IO_ADDR>$29</IO_ADDR>
<MEM_ADDR>$49</MEM_ADDR>
<OCR1BH0_MASK>0x01</OCR1BH0_MASK><OCR1BH1_MASK>0x02</OCR1BH1_MASK><OCR1BH2_MASK>0x04</OCR1BH2_MASK><OCR1BH3_MASK>0x08</OCR1BH3_MASK><OCR1BH4_MASK>0x10</OCR1BH4_MASK><OCR1BH5_MASK>0x20</OCR1BH5_MASK><OCR1BH6_MASK>0x40</OCR1BH6_MASK><OCR1BH7_MASK>0x80</OCR1BH7_MASK></OCR1BH>
<OCR1BL>
<IO_ADDR>$28</IO_ADDR>
<MEM_ADDR>$48</MEM_ADDR>
<OCR1BL0_MASK>0x01</OCR1BL0_MASK><OCR1BL1_MASK>0x02</OCR1BL1_MASK><OCR1BL2_MASK>0x04</OCR1BL2_MASK><OCR1BL3_MASK>0x08</OCR1BL3_MASK><OCR1BL4_MASK>0x10</OCR1BL4_MASK><OCR1BL5_MASK>0x20</OCR1BL5_MASK><OCR1BL6_MASK>0x40</OCR1BL6_MASK><OCR1BL7_MASK>0x80</OCR1BL7_MASK></OCR1BL>
<TCCR2>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<CS20_MASK>0x01</CS20_MASK><CS21_MASK>0x02</CS21_MASK><CS22_MASK>0x04</CS22_MASK><WGM21_MASK>0x08</WGM21_MASK><COM20_MASK>0x10</COM20_MASK><COM21_MASK>0x20</COM21_MASK><WGM20_MASK>0x40</WGM20_MASK><FOC2_MASK>0x80</FOC2_MASK></TCCR2>
<ASSR>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<TCR2UB_MASK>0x01</TCR2UB_MASK><OCR2UB_MASK>0x02</OCR2UB_MASK><TCN2UB_MASK>0x04</TCN2UB_MASK><AS2_MASK>0x08</AS2_MASK></ASSR>
<ICR1H>
<IO_ADDR>$25</IO_ADDR>
<MEM_ADDR>$45</MEM_ADDR>
<ICR1H0_MASK>0x01</ICR1H0_MASK><ICR1H1_MASK>0x02</ICR1H1_MASK><ICR1H2_MASK>0x04</ICR1H2_MASK><ICR1H3_MASK>0x08</ICR1H3_MASK><ICR1H4_MASK>0x10</ICR1H4_MASK><ICR1H5_MASK>0x20</ICR1H5_MASK><ICR1H6_MASK>0x40</ICR1H6_MASK><ICR1H7_MASK>0x80</ICR1H7_MASK></ICR1H>
<ICR1L>
<IO_ADDR>$24</IO_ADDR>
<MEM_ADDR>$44</MEM_ADDR>
<ICR1L0_MASK>0x01</ICR1L0_MASK><ICR1L1_MASK>0x02</ICR1L1_MASK><ICR1L2_MASK>0x04</ICR1L2_MASK><ICR1L3_MASK>0x08</ICR1L3_MASK><ICR1L4_MASK>0x10</ICR1L4_MASK><ICR1L5_MASK>0x20</ICR1L5_MASK><ICR1L6_MASK>0x40</ICR1L6_MASK><ICR1L7_MASK>0x80</ICR1L7_MASK></ICR1L>
<TCNT2>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<TCNT2_0_MASK>0x01</TCNT2_0_MASK><TCNT2_1_MASK>0x02</TCNT2_1_MASK><TCNT2_2_MASK>0x04</TCNT2_2_MASK><TCNT2_3_MASK>0x08</TCNT2_3_MASK><TCNT2_4_MASK>0x10</TCNT2_4_MASK><TCNT2_5_MASK>0x20</TCNT2_5_MASK><TCNT2_6_MASK>0x40</TCNT2_6_MASK><TCNT2_7_MASK>0x80</TCNT2_7_MASK></TCNT2>
<OCR2>
<IO_ADDR>$22</IO_ADDR>
<MEM_ADDR>$42</MEM_ADDR>
<OCR2_0_MASK>0x01</OCR2_0_MASK><OCR2_1_MASK>0x02</OCR2_1_MASK><OCR2_2_MASK>0x04</OCR2_2_MASK><OCR2_3_MASK>0x08</OCR2_3_MASK><OCR2_4_MASK>0x10</OCR2_4_MASK><OCR2_5_MASK>0x20</OCR2_5_MASK><OCR2_6_MASK>0x40</OCR2_6_MASK><OCR2_7_MASK>0x80</OCR2_7_MASK></OCR2>
<WDTCR>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<WDP0_MASK>0x01</WDP0_MASK><WDP1_MASK>0x02</WDP1_MASK><WDP2_MASK>0x04</WDP2_MASK><WDE_MASK>0x08</WDE_MASK><WDTOE_MASK>0x10</WDTOE_MASK></WDTCR>
<UBRR0H>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<UBRR8_MASK>0x01</UBRR8_MASK><UBRR9_MASK>0x02</UBRR9_MASK><UBRR10_MASK>0x04</UBRR10_MASK><UBRR11_MASK>0x08</UBRR11_MASK><URSEL_MASK>0x80</URSEL_MASK></UBRR0H>
<UCSR0C>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<UCPOL0_MASK>0x01</UCPOL0_MASK><UCSZ00_MASK>0x02</UCSZ00_MASK><UCSZ01_MASK>0x04</UCSZ01_MASK><USBS0_MASK>0x08</USBS0_MASK><UPM00_MASK>0x10</UPM00_MASK><UPM01_MASK>0x20</UPM01_MASK><UMSEL0_MASK>0x40</UMSEL0_MASK><URSEL0_MASK>0x80</URSEL0_MASK></UCSR0C>
<EEARH>
<IO_ADDR>$1F</IO_ADDR>
<MEM_ADDR>$3F</MEM_ADDR>
<EEAR8_MASK>0x01</EEAR8_MASK></EEARH>
<EEARL>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<EEAR0_MASK>0x01</EEAR0_MASK><EEAR1_MASK>0x02</EEAR1_MASK><EEAR2_MASK>0x04</EEAR2_MASK><EEAR3_MASK>0x08</EEAR3_MASK><EEAR4_MASK>0x10</EEAR4_MASK><EEAR5_MASK>0x20</EEAR5_MASK><EEAR6_MASK>0x40</EEAR6_MASK><EEAR7_MASK>0x80</EEAR7_MASK></EEARL>
<EEDR>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<EEDR0_MASK>0x01</EEDR0_MASK><EEDR1_MASK>0x02</EEDR1_MASK><EEDR2_MASK>0x04</EEDR2_MASK><EEDR3_MASK>0x08</EEDR3_MASK><EEDR4_MASK>0x10</EEDR4_MASK><EEDR5_MASK>0x20</EEDR5_MASK><EEDR6_MASK>0x40</EEDR6_MASK><EEDR7_MASK>0x80</EEDR7_MASK></EEDR>
<EECR>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<EERE_MASK>0x01</EERE_MASK><EEWE_MASK>0x02</EEWE_MASK><EEMWE_MASK>0x04</EEMWE_MASK><EERIE_MASK>0x08</EERIE_MASK></EECR>
<PORTA>
<IO_ADDR>$1B</IO_ADDR>
<MEM_ADDR>$3B</MEM_ADDR>
<MASK>$ff</MASK>
<PORTA0_MASK>0x01</PORTA0_MASK><PORTA1_MASK>0x02</PORTA1_MASK><PORTA2_MASK>0x04</PORTA2_MASK><PORTA3_MASK>0x08</PORTA3_MASK><PORTA4_MASK>0x10</PORTA4_MASK><PORTA5_MASK>0x20</PORTA5_MASK><PORTA6_MASK>0x40</PORTA6_MASK><PORTA7_MASK>0x80</PORTA7_MASK></PORTA>
<DDRA>
<IO_ADDR>$1A</IO_ADDR>
<MEM_ADDR>$3A</MEM_ADDR>
<DDA0_MASK>0x01</DDA0_MASK><DDA1_MASK>0x02</DDA1_MASK><DDA2_MASK>0x04</DDA2_MASK><DDA3_MASK>0x08</DDA3_MASK><DDA4_MASK>0x10</DDA4_MASK><DDA5_MASK>0x20</DDA5_MASK><DDA6_MASK>0x40</DDA6_MASK><DDA7_MASK>0x80</DDA7_MASK></DDRA>
<PINA>
<IO_ADDR>$19</IO_ADDR>
<MEM_ADDR>$39</MEM_ADDR>
<PINA0_MASK>0x01</PINA0_MASK><PINA1_MASK>0x02</PINA1_MASK><PINA2_MASK>0x04</PINA2_MASK><PINA3_MASK>0x08</PINA3_MASK><PINA4_MASK>0x10</PINA4_MASK><PINA5_MASK>0x20</PINA5_MASK><PINA6_MASK>0x40</PINA6_MASK><PINA7_MASK>0x80</PINA7_MASK></PINA>
<PORTB>
<IO_ADDR>$18</IO_ADDR>
<MEM_ADDR>$38</MEM_ADDR>
<MASK>$ff</MASK>
<PORTB0_MASK>0x01</PORTB0_MASK><PORTB1_MASK>0x02</PORTB1_MASK><PORTB2_MASK>0x04</PORTB2_MASK><PORTB3_MASK>0x08</PORTB3_MASK><PORTB4_MASK>0x10</PORTB4_MASK><PORTB5_MASK>0x20</PORTB5_MASK><PORTB6_MASK>0x40</PORTB6_MASK><PORTB7_MASK>0x80</PORTB7_MASK></PORTB>
<DDRB>
<IO_ADDR>$17</IO_ADDR>
<MEM_ADDR>$37</MEM_ADDR>
<DDB0_MASK>0x01</DDB0_MASK><DDB1_MASK>0x02</DDB1_MASK><DDB2_MASK>0x04</DDB2_MASK><DDB3_MASK>0x08</DDB3_MASK><DDB4_MASK>0x10</DDB4_MASK><DDB5_MASK>0x20</DDB5_MASK><DDB6_MASK>0x40</DDB6_MASK><DDB7_MASK>0x80</DDB7_MASK></DDRB>
<PINB>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<PINB0_MASK>0x01</PINB0_MASK><PINB1_MASK>0x02</PINB1_MASK><PINB2_MASK>0x04</PINB2_MASK><PINB3_MASK>0x08</PINB3_MASK><PINB4_MASK>0x10</PINB4_MASK><PINB5_MASK>0x20</PINB5_MASK><PINB6_MASK>0x40</PINB6_MASK><PINB7_MASK>0x80</PINB7_MASK></PINB>
<PORTC>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<MASK>$ff</MASK>
<PORTC0_MASK>0x01</PORTC0_MASK><PORTC1_MASK>0x02</PORTC1_MASK><PORTC2_MASK>0x04</PORTC2_MASK><PORTC3_MASK>0x08</PORTC3_MASK><PORTC4_MASK>0x10</PORTC4_MASK><PORTC5_MASK>0x20</PORTC5_MASK><PORTC6_MASK>0x40</PORTC6_MASK><PORTC7_MASK>0x80</PORTC7_MASK></PORTC>
<DDRC>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<DDC0_MASK>0x01</DDC0_MASK><DDC1_MASK>0x02</DDC1_MASK><DDC2_MASK>0x04</DDC2_MASK><DDC3_MASK>0x08</DDC3_MASK><DDC4_MASK>0x10</DDC4_MASK><DDC5_MASK>0x20</DDC5_MASK><DDC6_MASK>0x40</DDC6_MASK><DDC7_MASK>0x80</DDC7_MASK></DDRC>
<PINC>
<IO_ADDR>$13</IO_ADDR>
<MEM_ADDR>$33</MEM_ADDR>
<PINC0_MASK>0x01</PINC0_MASK><PINC1_MASK>0x02</PINC1_MASK><PINC2_MASK>0x04</PINC2_MASK><PINC3_MASK>0x08</PINC3_MASK><PINC4_MASK>0x10</PINC4_MASK><PINC5_MASK>0x20</PINC5_MASK><PINC6_MASK>0x40</PINC6_MASK><PINC7_MASK>0x80</PINC7_MASK></PINC>
<PORTD>
<IO_ADDR>$12</IO_ADDR>
<MEM_ADDR>$32</MEM_ADDR>
<MASK>$ff</MASK>
<PORTD0_MASK>0x01</PORTD0_MASK><PORTD1_MASK>0x02</PORTD1_MASK><PORTD2_MASK>0x04</PORTD2_MASK><PORTD3_MASK>0x08</PORTD3_MASK><PORTD4_MASK>0x10</PORTD4_MASK><PORTD5_MASK>0x20</PORTD5_MASK><PORTD6_MASK>0x40</PORTD6_MASK><PORTD7_MASK>0x80</PORTD7_MASK></PORTD>
<DDRD>
<IO_ADDR>$11</IO_ADDR>
<MEM_ADDR>$31</MEM_ADDR>
<DDD0_MASK>0x01</DDD0_MASK><DDD1_MASK>0x02</DDD1_MASK><DDD2_MASK>0x04</DDD2_MASK><DDD3_MASK>0x08</DDD3_MASK><DDD4_MASK>0x10</DDD4_MASK><DDD5_MASK>0x20</DDD5_MASK><DDD6_MASK>0x40</DDD6_MASK><DDD7_MASK>0x80</DDD7_MASK></DDRD>
<PIND>
<IO_ADDR>$10</IO_ADDR>
<MEM_ADDR>$30</MEM_ADDR>
<PIND0_MASK>0x01</PIND0_MASK><PIND1_MASK>0x02</PIND1_MASK><PIND2_MASK>0x04</PIND2_MASK><PIND3_MASK>0x08</PIND3_MASK><PIND4_MASK>0x10</PIND4_MASK><PIND5_MASK>0x20</PIND5_MASK><PIND6_MASK>0x40</PIND6_MASK><PIND7_MASK>0x80</PIND7_MASK></PIND>
<SPDR>
<IO_ADDR>$0F</IO_ADDR>
<MEM_ADDR>$2F</MEM_ADDR>
<SPDR0_MASK>0x01</SPDR0_MASK><SPDR1_MASK>0x02</SPDR1_MASK><SPDR2_MASK>0x04</SPDR2_MASK><SPDR3_MASK>0x08</SPDR3_MASK><SPDR4_MASK>0x10</SPDR4_MASK><SPDR5_MASK>0x20</SPDR5_MASK><SPDR6_MASK>0x40</SPDR6_MASK><SPDR7_MASK>0x80</SPDR7_MASK></SPDR>
<SPSR>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<SPI2X_MASK>0x01</SPI2X_MASK><WCOL_MASK>0x40</WCOL_MASK><SPIF_MASK>0x80</SPIF_MASK></SPSR>
<SPCR>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<SPR0_MASK>0x01</SPR0_MASK><SPR1_MASK>0x02</SPR1_MASK><CPHA_MASK>0x04</CPHA_MASK><CPOL_MASK>0x08</CPOL_MASK><MSTR_MASK>0x10</MSTR_MASK><DORD_MASK>0x20</DORD_MASK><SPE_MASK>0x40</SPE_MASK><SPIE_MASK>0x80</SPIE_MASK></SPCR>
<UDR0>
<IO_ADDR>$0C</IO_ADDR>
<MEM_ADDR>$2C</MEM_ADDR>
<UDR0-0_MASK>0x01</UDR0-0_MASK><UDR0-1_MASK>0x02</UDR0-1_MASK><UDR0-2_MASK>0x04</UDR0-2_MASK><UDR0-3_MASK>0x08</UDR0-3_MASK><UDR0-4_MASK>0x10</UDR0-4_MASK><UDR0-5_MASK>0x20</UDR0-5_MASK><UDR0-6_MASK>0x40</UDR0-6_MASK><UDR0-7_MASK>0x80</UDR0-7_MASK></UDR0>
<UCSR0A>
<IO_ADDR>$0B</IO_ADDR>
<MEM_ADDR>$2B</MEM_ADDR>
<MPCM0_MASK>0x01</MPCM0_MASK><U2X0_MASK>0x02</U2X0_MASK><UPE0_MASK>0x04</UPE0_MASK><DOR0_MASK>0x08</DOR0_MASK><FE0_MASK>0x10</FE0_MASK><UDRE0_MASK>0x20</UDRE0_MASK><TXC0_MASK>0x40</TXC0_MASK><RXC0_MASK>0x80</RXC0_MASK></UCSR0A>
<UCSR0B>
<IO_ADDR>$0A</IO_ADDR>
<MEM_ADDR>$2A</MEM_ADDR>
<TXB80_MASK>0x01</TXB80_MASK><RXB80_MASK>0x02</RXB80_MASK><UCSZ02_MASK>0x04</UCSZ02_MASK><TXEN0_MASK>0x08</TXEN0_MASK><RXEN0_MASK>0x10</RXEN0_MASK><UDRIE0_MASK>0x20</UDRIE0_MASK><TXCIE0_MASK>0x40</TXCIE0_MASK><RXCIE0_MASK>0x80</RXCIE0_MASK></UCSR0B>
<UBRR0L>
<IO_ADDR>$09</IO_ADDR>
<MEM_ADDR>$29</MEM_ADDR>
<UBRR0_MASK>0x01</UBRR0_MASK><UBRR1_MASK>0x02</UBRR1_MASK><UBRR2_MASK>0x04</UBRR2_MASK><UBRR3_MASK>0x08</UBRR3_MASK><UBRR4_MASK>0x10</UBRR4_MASK><UBRR5_MASK>0x20</UBRR5_MASK><UBRR6_MASK>0x40</UBRR6_MASK><UBRR7_MASK>0x80</UBRR7_MASK></UBRR0L>
<ACSR>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
<ACIS0_MASK>0x01</ACIS0_MASK><ACIS1_MASK>0x02</ACIS1_MASK><ACIC_MASK>0x04</ACIC_MASK><ACIE_MASK>0x08</ACIE_MASK><ACI_MASK>0x10</ACI_MASK><ACO_MASK>0x20</ACO_MASK><ACBG_MASK>0x40</ACBG_MASK><ACD_MASK>0x80</ACD_MASK></ACSR>
<PORTE>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
<PORTE0_MASK>0x01</PORTE0_MASK><PORTE1_MASK>0x02</PORTE1_MASK><PORTE2_MASK>0x04</PORTE2_MASK></PORTE>
<DDRE>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
<DDE0_MASK>0x01</DDE0_MASK><DDE1_MASK>0x02</DDE1_MASK><DDE2_MASK>0x04</DDE2_MASK></DDRE>
<PINE>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<PINE0_MASK>0x01</PINE0_MASK><PINE1_MASK>0x02</PINE1_MASK><PINE2_MASK>0x04</PINE2_MASK></PINE>
<OSCCAL>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<CAL0_MASK>0x01</CAL0_MASK><CAL1_MASK>0x02</CAL1_MASK><CAL2_MASK>0x04</CAL2_MASK><CAL3_MASK>0x08</CAL3_MASK><CAL4_MASK>0x10</CAL4_MASK><CAL5_MASK>0x20</CAL5_MASK><CAL6_MASK>0x40</CAL6_MASK></OSCCAL>
<OCDR>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
</OCDR>
<UDR1>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<UDR1-0_MASK>0x01</UDR1-0_MASK><UDR1-1_MASK>0x02</UDR1-1_MASK><UDR1-2_MASK>0x04</UDR1-2_MASK><UDR1-3_MASK>0x08</UDR1-3_MASK><UDR1-4_MASK>0x10</UDR1-4_MASK><UDR1-5_MASK>0x20</UDR1-5_MASK><UDR1-6_MASK>0x40</UDR1-6_MASK><UDR1-7_MASK>0x80</UDR1-7_MASK></UDR1>
<UCSR1A>
<IO_ADDR>$02</IO_ADDR>
<MEM_ADDR>$22</MEM_ADDR>
<MPCM1_MASK>0x01</MPCM1_MASK><U2X1_MASK>0x02</U2X1_MASK><UPE1_MASK>0x04</UPE1_MASK><DOR1_MASK>0x08</DOR1_MASK><FE1_MASK>0x10</FE1_MASK><UDRE1_MASK>0x20</UDRE1_MASK><TXC1_MASK>0x40</TXC1_MASK><RXC1_MASK>0x80</RXC1_MASK></UCSR1A>
<UCSR1B>
<IO_ADDR>$01</IO_ADDR>
<MEM_ADDR>$21</MEM_ADDR>
<TXB81_MASK>0x01</TXB81_MASK><RXB81_MASK>0x02</RXB81_MASK><UCSZ12_MASK>0x04</UCSZ12_MASK><TXEN1_MASK>0x08</TXEN1_MASK><RXEN1_MASK>0x10</RXEN1_MASK><UDRIE1_MASK>0x20</UDRIE1_MASK><TXCIE1_MASK>0x40</TXCIE1_MASK><RXCIE1_MASK>0x80</RXCIE1_MASK></UCSR1B>
<UBRR1L>
<IO_ADDR>$00</IO_ADDR>
<MEM_ADDR>$20</MEM_ADDR>
<UBRR1L0_MASK>0x01</UBRR1L0_MASK><UBRR1L1_MASK>0x02</UBRR1L1_MASK><UBRR1L2_MASK>0x04</UBRR1L2_MASK><UBRR1L3_MASK>0x08</UBRR1L3_MASK><UBRR1L4_MASK>0x10</UBRR1L4_MASK><UBRR1L5_MASK>0x20</UBRR1L5_MASK><UBRR1L6_MASK>0x40</UBRR1L6_MASK><UBRR1L7_MASK>0x80</UBRR1L7_MASK></UBRR1L>
</IO_MEMORY>
<BOOT_CONFIG>
<NRWW_START_ADDR>x</NRWW_START_ADDR>
<NRWW_STOP_ADDR>x</NRWW_STOP_ADDR>
<RWW_START_ADDR>x</RWW_START_ADDR>
<RWW_STOP_ADDR>x</RWW_STOP_ADDR>
<PAGESIZE>64</PAGESIZE>
<BOOTSZMODE1>
<BOOTSIZE>x</BOOTSIZE>
<PAGES>x</PAGES>
<APPSTART>x</APPSTART>
<BOOTSTART>x</BOOTSTART>
<BOOTRESET>$1E00</BOOTRESET>
</BOOTSZMODE1>
</BOOT_CONFIG>
</MEMORY>
<IO_MODULE><MODULE_LIST>[SPI:PORTA:PORTB:PORTC:PORTD:PORTE:EEPROM:TIMER_COUNTER_0:TIMER_COUNTER_1:WATCHDOG:USART0:USART1:TIMER_COUNTER_2:ANALOG_COMPARATOR:CPU:BOOT_LOAD:EXTERNAL_INTERRUPT]</MODULE_LIST><SPI>
<LIST>[SPDR:SPSR:SPCR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID>SPI_01</ID>
<TEXT>The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode</TEXT>
<SPDR>
<NAME>SPDR</NAME>
<DESCRIPTION>SPI Data Register</DESCRIPTION>
<TEXT>The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.</TEXT>
<IO_ADDR>$0F</IO_ADDR>
<MEM_ADDR>$2F</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SPDR7</NAME>
<DESCRIPTION>SPI Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SPDR6</NAME>
<DESCRIPTION>SPI Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SPDR5</NAME>
<DESCRIPTION>SPI Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SPDR4</NAME>
<DESCRIPTION>SPI Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SPDR3</NAME>
<DESCRIPTION>SPI Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SPDR2</NAME>
<DESCRIPTION>SPI Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SPDR1</NAME>
<DESCRIPTION>SPI Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPDR0</NAME>
<DESCRIPTION>SPI Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPDR>
<SPSR>
<NAME>SPSR</NAME>
<DESCRIPTION>SPI Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIF</NAME>
<DESCRIPTION>SPI Interrupt Flag</DESCRIPTION>
<TEXT>When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WCOL</NAME>
<DESCRIPTION>Write Collision Flag</DESCRIPTION>
<TEXT>The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT0>
<NAME>SPI2X</NAME>
<DESCRIPTION>Double SPI Speed Bit</DESCRIPTION>
<TEXT>When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPSR>
<SPCR>
<NAME>SPCR</NAME>
<DESCRIPTION>SPI Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIE</NAME>
<DESCRIPTION>SPI Interrupt Enable</DESCRIPTION>
<TEXT>This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SPE</NAME>
<DESCRIPTION>SPI Enable</DESCRIPTION>
<TEXT>When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DORD</NAME>
<DESCRIPTION>Data Order</DESCRIPTION>
<TEXT>When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>MSTR</NAME>
<DESCRIPTION>Master/Slave Select</DESCRIPTION>
<TEXT>This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CPOL</NAME>
<DESCRIPTION>Clock polarity</DESCRIPTION>
<TEXT>When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CPHA</NAME>
<DESCRIPTION>Clock Phase</DESCRIPTION>
<TEXT>Refer to Figure 36 or Figure 37 for the functionality of this bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SPR1</NAME>
<DESCRIPTION>SPI Clock Rate Select 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPR0</NAME>
<DESCRIPTION>SPI Clock Rate Select 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPCR>
</SPI>
<PORTA>
<LIST>[PORTA:DDRA:PINA]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTA>
<NAME>PORTA</NAME>
<DESCRIPTION>Port A Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1B</IO_ADDR>
<MEM_ADDR>$3B</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTA7</NAME>
<DESCRIPTION>Port A Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTA6</NAME>
<DESCRIPTION>Port A Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTA5</NAME>
<DESCRIPTION>Port A Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTA4</NAME>
<DESCRIPTION>Port A Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTA3</NAME>
<DESCRIPTION>Port A Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTA2</NAME>
<DESCRIPTION>Port A Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTA1</NAME>
<DESCRIPTION>Port A Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTA0</NAME>
<DESCRIPTION>Port A Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTA>
<DDRA>
<NAME>DDRA</NAME>
<DESCRIPTION>Port A Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1A</IO_ADDR>
<MEM_ADDR>$3A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDA7</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDA6</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDA5</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDA4</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDA3</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDA2</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDA1</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDA0</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRA>
<PINA>
<NAME>PINA</NAME>
<DESCRIPTION>Port A Input Pins</DESCRIPTION>
<TEXT>The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$19</IO_ADDR>
<MEM_ADDR>$39</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINA7</NAME>
<DESCRIPTION>Input Pins, Port A bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINA6</NAME>
<DESCRIPTION>Input Pins, Port A bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINA5</NAME>
<DESCRIPTION>Input Pins, Port A bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINA4</NAME>
<DESCRIPTION>Input Pins, Port A bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINA3</NAME>
<DESCRIPTION>Input Pins, Port A bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINA2</NAME>
<DESCRIPTION>Input Pins, Port A bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINA1</NAME>
<DESCRIPTION>Input Pins, Port A bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINA0</NAME>
<DESCRIPTION>Input Pins, Port A bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT0>
</PINA>
</PORTA>
<PORTB>
<LIST>[PORTB:DDRB:PINB]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTB>
<NAME>PORTB</NAME>
<DESCRIPTION>Port B Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$18</IO_ADDR>
<MEM_ADDR>$38</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTB7</NAME>
<DESCRIPTION>Port B Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTB6</NAME>
<DESCRIPTION>Port B Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTB5</NAME>
<DESCRIPTION>Port B Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTB4</NAME>
<DESCRIPTION>Port B Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTB3</NAME>
<DESCRIPTION>Port B Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTB2</NAME>
<DESCRIPTION>Port B Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTB1</NAME>
<DESCRIPTION>Port B Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTB0</NAME>
<DESCRIPTION>Port B Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTB>
<DDRB>
<NAME>DDRB</NAME>
<DESCRIPTION>Port B Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$17</IO_ADDR>
<MEM_ADDR>$37</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDB7</NAME>
<DESCRIPTION>Port B Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDB6</NAME>
<DESCRIPTION>Port B Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDB5</NAME>
<DESCRIPTION>Port B Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDB4</NAME>
<DESCRIPTION>Port B Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDB3</NAME>
<DESCRIPTION>Port B Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDB2</NAME>
<DESCRIPTION>Port B Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDB1</NAME>
<DESCRIPTION>Port B Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDB0</NAME>
<DESCRIPTION>Port B Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRB>
<PINB>
<NAME>PINB</NAME>
<DESCRIPTION>Port B Input Pins</DESCRIPTION>
<TEXT>The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINB7</NAME>
<DESCRIPTION>Port B Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINB6</NAME>
<DESCRIPTION>Port B Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINB5</NAME>
<DESCRIPTION>Port B Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINB4</NAME>
<DESCRIPTION>Port B Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINB3</NAME>
<DESCRIPTION>Port B Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINB2</NAME>
<DESCRIPTION>Port B Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINB1</NAME>
<DESCRIPTION>Port B Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINB0</NAME>
<DESCRIPTION>Port B Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINB>
</PORTB>
<PORTC>
<LIST>[PORTC:DDRC:PINC]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTC>
<NAME>PORTC</NAME>
<DESCRIPTION>Port C Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTC7</NAME>
<DESCRIPTION>Port C Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTC6</NAME>
<DESCRIPTION>Port C Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTC5</NAME>
<DESCRIPTION>Port C Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTC4</NAME>
<DESCRIPTION>Port C Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTC3</NAME>
<DESCRIPTION>Port C Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTC2</NAME>
<DESCRIPTION>Port C Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTC1</NAME>
<DESCRIPTION>Port C Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTC0</NAME>
<DESCRIPTION>Port C Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTC>
<DDRC>
<NAME>DDRC</NAME>
<DESCRIPTION>Port C Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDC7</NAME>
<DESCRIPTION>Port C Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDC6</NAME>
<DESCRIPTION>Port C Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDC5</NAME>
<DESCRIPTION>Port C Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDC4</NAME>
<DESCRIPTION>Port C Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDC3</NAME>
<DESCRIPTION>Port C Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDC2</NAME>
<DESCRIPTION>Port C Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDC1</NAME>
<DESCRIPTION>Port C Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDC0</NAME>
<DESCRIPTION>Port C Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRC>
<PINC>
<NAME>PINC</NAME>
<DESCRIPTION>Port C Input Pins</DESCRIPTION>
<TEXT>The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$13</IO_ADDR>
<MEM_ADDR>$33</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINC7</NAME>
<DESCRIPTION>Port C Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINC6</NAME>
<DESCRIPTION>Port C Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINC5</NAME>
<DESCRIPTION>Port C Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINC4</NAME>
<DESCRIPTION>Port C Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINC3</NAME>
<DESCRIPTION>Port C Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINC2</NAME>
<DESCRIPTION>Port C Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINC1</NAME>
<DESCRIPTION>Port C Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINC0</NAME>
<DESCRIPTION>Port C Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINC>
</PORTC>
<PORTD>
<LIST>[PORTD:DDRD:PIND]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTD>
<NAME>PORTD</NAME>
<DESCRIPTION>Port D Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$12</IO_ADDR>
<MEM_ADDR>$32</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTD7</NAME>
<DESCRIPTION>Port D Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTD6</NAME>
<DESCRIPTION>Port D Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTD5</NAME>
<DESCRIPTION>Port D Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTD4</NAME>
<DESCRIPTION>Port D Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTD3</NAME>
<DESCRIPTION>Port D Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTD2</NAME>
<DESCRIPTION>Port D Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTD1</NAME>
<DESCRIPTION>Port D Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTD0</NAME>
<DESCRIPTION>Port D Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTD>
<DDRD>
<NAME>DDRD</NAME>
<DESCRIPTION>Port D Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$11</IO_ADDR>
<MEM_ADDR>$31</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDD7</NAME>
<DESCRIPTION>Port D Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDD6</NAME>
<DESCRIPTION>Port D Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDD5</NAME>
<DESCRIPTION>Port D Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDD4</NAME>
<DESCRIPTION>Port D Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDD3</NAME>
<DESCRIPTION>Port D Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDD2</NAME>
<DESCRIPTION>Port D Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDD1</NAME>
<DESCRIPTION>Port D Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDD0</NAME>
<DESCRIPTION>Port D Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRD>
<PIND>
<NAME>PIND</NAME>
<DESCRIPTION>Port D Input Pins</DESCRIPTION>
<TEXT>The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$10</IO_ADDR>
<MEM_ADDR>$30</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PIND7</NAME>
<DESCRIPTION>Port D Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PIND6</NAME>
<DESCRIPTION>Port D Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PIND5</NAME>
<DESCRIPTION>Port D Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PIND4</NAME>
<DESCRIPTION>Port D Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PIND3</NAME>
<DESCRIPTION>Port D Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PIND2</NAME>
<DESCRIPTION>Port D Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PIND1</NAME>
<DESCRIPTION>Port D Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PIND0</NAME>
<DESCRIPTION>Port D Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PIND>
</PORTD>
<PORTE>
<LIST>[PORTE:DDRE:PINE]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTE>
<NAME>PORTE</NAME>
<DESCRIPTION>Port E Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT2>
<NAME>PORTE2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTE1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTE0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTE>
<DDRE>
<NAME>DDRE</NAME>
<DESCRIPTION>Port E Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT2>
<NAME>DDE2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDE1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDE0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRE>
<PINE>
<NAME>PINE</NAME>
<DESCRIPTION>Port E Input Pins</DESCRIPTION>
<TEXT/>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT2>
<NAME>PINE2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINE1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINE0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINE>
</PORTE>
<EEPROM>
<LIST>[EEARH:EEARL:EEDR:EECR]</LIST>
<LINK>[EEARH:EEARL]</LINK>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT>EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute</TEXT>
<EEARH>
<NAME>EEARH</NAME>
<DESCRIPTION>EEPROM Address Register High Byte</DESCRIPTION>
<TEXT>Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. </TEXT>
<IO_ADDR>$1F</IO_ADDR>
<MEM_ADDR>$3F</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT0>
<NAME>EEAR8</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARH>
<EEARL>
<NAME>EEARL</NAME>
<DESCRIPTION>EEPROM Address Register Low Byte</DESCRIPTION>
<TEXT>Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. </TEXT>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEAR7</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEAR6</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEAR5</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEAR4</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEAR3</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEAR2</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEAR1</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEAR0</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARL>
<EEDR>
<NAME>EEDR</NAME>
<DESCRIPTION>EEPROM Data Register</DESCRIPTION>
<TEXT>For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.</TEXT>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEDR7</NAME>
<DESCRIPTION>EEPROM Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEDR6</NAME>
<DESCRIPTION>EEPROM Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEDR5</NAME>
<DESCRIPTION>EEPROM Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEDR4</NAME>
<DESCRIPTION>EEPROM Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEDR3</NAME>
<DESCRIPTION>EEPROM Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEDR2</NAME>
<DESCRIPTION>EEPROM Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEDR1</NAME>
<DESCRIPTION>EEPROM Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEDR0</NAME>
<DESCRIPTION>EEPROM Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEDR>
<EECR>
<NAME>EECR</NAME>
<DESCRIPTION>EEPROM Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>EERIE</NAME>
<DESCRIPTION>EEPROM Ready Interrupt Enable</DESCRIPTION>
<TEXT>EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEMWE</NAME>
<ALIAS>EEWEE</ALIAS>
<DESCRIPTION>EEPROM Master Write Enable</DESCRIPTION>
<TEXT>The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEWE</NAME>
<DESCRIPTION>EEPROM Write Enable</DESCRIPTION>
<TEXT>The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EERE</NAME>
<DESCRIPTION>EEPROM Read Enable</DESCRIPTION>
<TEXT>The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EECR>
</EEPROM>
<TIMER_COUNTER_0>
<LIST>[TCCR0:TCNT0:OCR0:TIMSK:TIFR:SFIOR]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>At8pwm0_01</ID>
<TEXT/>
<TCCR0>
<NAME>TCCR0</NAME>
<DESCRIPTION>Timer/Counter Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC0</NAME>
<DESCRIPTION>Force Output Compare</DESCRIPTION>
<TEXT>The FOC0 bit is only active when the WGM bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate compare match is forced on the waveform generation unit. The OC0 output is changed accord-ing to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero.</TEXT>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WGM00</NAME>
<DESCRIPTION>Waveform Generation Mode 0</DESCRIPTION>
<TEXT>These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 51 and “Modes of Operation” on page 80. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM01</NAME>
<DESCRIPTION>Compare Match Output Mode 1</DESCRIPTION>
<TEXT>These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM)</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM00</NAME>
<DESCRIPTION>Compare match Output Mode 0</DESCRIPTION>
<TEXT>These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM)</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WGM01</NAME>
<DESCRIPTION>Waveform Generation Mode 1</DESCRIPTION>
<TEXT>These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 51 and “Modes of Operation” on page 80. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS02</NAME>
<DESCRIPTION>Clock Select 2</DESCRIPTION>
<TEXT>The three clock select bits select the clock source to be used by the Timer/Counter,</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS01</NAME>
<DESCRIPTION>Clock Select 1</DESCRIPTION>
<TEXT>The three clock select bits select the clock source to be used by the Timer/Counter,</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS00</NAME>
<DESCRIPTION>Clock Select 1</DESCRIPTION>
<TEXT>The three clock select bits select the clock source to be used by the Timer/Counter,</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0>
<TCNT0>
<NAME>TCNT0</NAME>
<DESCRIPTION>Timer/Counter Register </DESCRIPTION>
<TEXT>The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.</TEXT>
<IO_ADDR>$32</IO_ADDR>
<MEM_ADDR>$52</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT0_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT0_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT0_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT0_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT0_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT0_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT0_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT0_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT0>
<OCR0>
<NAME>OCR0</NAME>
<DESCRIPTION>Output Compare Register</DESCRIPTION>
<TEXT>The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.</TEXT>
<IO_ADDR>$31</IO_ADDR>
<MEM_ADDR>$51</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0>
<TIMSK>
<NAME>TIMSK</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>TOIE0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCIE0</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Match Interrupt register</DESCRIPTION>
<TEXT>When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e. when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK>
<TIFR>
<NAME>TIFR</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>TOV0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Flag</DESCRIPTION>
<TEXT>The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCF0</NAME>
<DESCRIPTION>Output Compare Flag 0</DESCRIPTION>
<TEXT>The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 - Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR>
<SFIOR>
<NAME>SFIOR</NAME>
<DESCRIPTION>Special Function IO Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT0>
<NAME>PSR10</NAME>
<DESCRIPTION>Prescaler Reset Timer/Counter1 and Timer/Counter0</DESCRIPTION>
<TEXT>When this bit is set (one)the Timer/Counter1 and Timer/Counter0 prescaler will be reset.The bit will be cleared by hard ware after the operation is performed.Writing a zero to this bit will have no effect.Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.This bit will always be read as zero.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SFIOR>
</TIMER_COUNTER_0>
<TIMER_COUNTER_1>
<LIST>[TIMSK:TIFR:TCCR1A:TCCR1B:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L]</LIST>
<LINK>[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L]</LINK>
<ICON>io_timer.bmp</ICON>
<ID>t16pwm1_05.xml</ID>
<TEXT/>
<TIMSK>
<NAME>TIMSK</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TOIE1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCIE1A</NAME>
<DESCRIPTION>Timer/Counter1 Output CompareA Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCIE1B</NAME>
<DESCRIPTION>Timer/Counter1 Output CompareB Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>TICIE1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Interrupt Enable</DESCRIPTION>
<TEXT>When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
</TIMSK>
<TIFR>
<NAME>TIFR</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TOV1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Flag</DESCRIPTION>
<TEXT>The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCF1A</NAME>
<DESCRIPTION>Output Compare Flag 1A</DESCRIPTION>
<TEXT>The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCF1B</NAME>
<DESCRIPTION>Output Compare Flag 1B</DESCRIPTION>
<TEXT>The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>ICF1</NAME>
<DESCRIPTION>Input Capture Flag 1</DESCRIPTION>
<TEXT>The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
</TIFR>
<TCCR1A>
<NAME>TCCR1A</NAME>
<DESCRIPTION>Timer/Counter1 Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2F</IO_ADDR>
<MEM_ADDR>$4F</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM1A1</NAME>
<DESCRIPTION>Compare Output Mode 1A, bit 1</DESCRIPTION>
<TEXT>The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM1A0</NAME>
<DESCRIPTION>Comparet Ouput Mode 1A, bit 0</DESCRIPTION>
<TEXT>The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM1B1</NAME>
<DESCRIPTION>Compare Output Mode 1B, bit 1</DESCRIPTION>
<TEXT>The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM1B0</NAME>
<DESCRIPTION>Compare Output Mode 1B, bit 0</DESCRIPTION>
<TEXT>The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>FOC1A</NAME>
<DESCRIPTION>Force Output Compare 1A</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0.If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM mod</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>FOC1B</NAME>
<DESCRIPTION>Force Output Compare 1B</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mode</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WGM11</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM10</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1A>
<TCCR1B>
<NAME>TCCR1B</NAME>
<DESCRIPTION>Timer/Counter1 Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ICNC1</NAME>
<DESCRIPTION>Input Capture 1 Noise Canceler</DESCRIPTION>
<TEXT>When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICES1</NAME>
<DESCRIPTION>Input Capture 1 Edge Select</DESCRIPTION>
<TEXT>While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>CTC1</NAME>
<DESCRIPTION>Clear Timer/Counter1 on Compare Match</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS12</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS11</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS10</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1B>
<TCNT1H>
<NAME>TCNT1H</NAME>
<DESCRIPTION>Timer/Counter1 High Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou</TEXT>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1H7</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1H6</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1H5</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1H4</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1H3</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1H2</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1H1</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1H0</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1H>
<TCNT1L>
<NAME>TCNT1L</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1L7</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1L6</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1L5</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1L4</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1L3</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1L2</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1L1</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1L0</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1L>
<OCR1AH>
<NAME>OCR1AH</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>$2B</IO_ADDR>
<MEM_ADDR>$4B</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AH7</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AH6</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AH5</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AH4</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AH3</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AH2</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AH1</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AH0</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1AH>
<OCR1AL>
<NAME>OCR1AL</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>$2A</IO_ADDR>
<MEM_ADDR>$4A</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AL7</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AL6</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AL5</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AL4</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AL3</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AL2</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AL1</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AL0</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1AL>
<OCR1BH>
<NAME>OCR1BH</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro</TEXT>
<IO_ADDR>$29</IO_ADDR>
<MEM_ADDR>$49</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1BH7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1BH6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1BH5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1BH4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1BH3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1BH2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1BH1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1BH0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1BH>
<OCR1BL>
<NAME>OCR1BL</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>$28</IO_ADDR>
<MEM_ADDR>$48</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1BL7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1BL6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1BL5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1BL4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1BL3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1BL2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1BL1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1BL0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1BL>
<ICR1H>
<NAME>ICR1H</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt</TEXT>
<IO_ADDR>$25</IO_ADDR>
<MEM_ADDR>$45</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR1H7</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR1H6</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR1H5</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR1H4</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR1H3</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR1H2</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR1H1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR1H0</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR1H>
<ICR1L>
<NAME>ICR1L</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter</TEXT>
<IO_ADDR>$24</IO_ADDR>
<MEM_ADDR>$44</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR1L7</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR1L6</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR1L5</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR1L4</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR1L3</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR1L2</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR1L1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR1L0</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR1L>
</TIMER_COUNTER_1>
<WATCHDOG>
<LIST>[WDTCR]</LIST>
<LINK/>
<ICON>io_watch.bmp</ICON>
<ID/>
<TEXT/>
<WDTCR>
<NAME>WDTCR</NAME>
<DESCRIPTION>Watchdog Timer Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>WDTOE</NAME>
<ALIAS>WDDE</ALIAS>
<DESCRIPTION>RW</DESCRIPTION>
<TEXT>This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WDE</NAME>
<DESCRIPTION>Watch Dog Enable</DESCRIPTION>
<TEXT>When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>WDP2</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WDP1</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WDP0</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</WDTCR>
</WATCHDOG>
<USART0>
<LIST>[UDR0:UCSR0A:UCSR0B:UCSR0C:UBRR0H:UBRR0L]</LIST>
<LINK>[UBRR0H:UBRR0L]</LINK>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communica</TEXT>
<UDR0>
<NAME>UDR0</NAME>
<ALIAS>UDR</ALIAS>
<DESCRIPTION>USART I/O Data Register</DESCRIPTION>
<TEXT>The UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.</TEXT>
<IO_ADDR>$0C</IO_ADDR>
<MEM_ADDR>$2C</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UDR0-7</NAME>
<DESCRIPTION>USART I/O Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UDR0-6</NAME>
<DESCRIPTION>USART I/O Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDR0-5</NAME>
<DESCRIPTION>USART I/O Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UDR0-4</NAME>
<DESCRIPTION>USART I/O Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UDR0-3</NAME>
<DESCRIPTION>USART I/O Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UDR0-2</NAME>
<DESCRIPTION>USART I/O Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UDR0-1</NAME>
<DESCRIPTION>USART I/O Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UDR0-0</NAME>
<DESCRIPTION>USART I/O Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UDR0>
<UCSR0A>
<NAME>UCSR0A</NAME>
<ALIAS>USR</ALIAS>
<DESCRIPTION>USART Control and Status Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0B</IO_ADDR>
<MEM_ADDR>$2B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXC0</NAME>
<ALIAS>RXC</ALIAS>
<DESCRIPTION>USART Receive Complete</DESCRIPTION>
<TEXT>This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXC0</NAME>
<ALIAS>TXC</ALIAS>
<DESCRIPTION>USART Transmitt Complete</DESCRIPTION>
<TEXT>This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRE0</NAME>
<ALIAS>UDRE</ALIAS>
<DESCRIPTION>USART Data Register Empty</DESCRIPTION>
<TEXT>This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>FE0</NAME>
<ALIAS>FE</ALIAS>
<DESCRIPTION>Framing Error</DESCRIPTION>
<TEXT>This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DOR0</NAME>
<ALIAS>DOR</ALIAS>
<DESCRIPTION>Data overRun</DESCRIPTION>
<TEXT>This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. </TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UPE0</NAME>
<DESCRIPTION>Parity Error</DESCRIPTION>
<TEXT>This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>U2X0</NAME>
<ALIAS>U2X</ALIAS>
<DESCRIPTION>Double the USART transmission speed</DESCRIPTION>
<TEXT>This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MPCM0</NAME>
<DESCRIPTION>Multi-processor Communication Mode</DESCRIPTION>
<TEXT>This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR0A>
<UCSR0B>
<NAME>UCSR0B</NAME>
<ALIAS>UCR</ALIAS>
<DESCRIPTION>USART Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0A</IO_ADDR>
<MEM_ADDR>$2A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXCIE0</NAME>
<ALIAS>RXCIE</ALIAS>
<DESCRIPTION>RX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXCIE0</NAME>
<ALIAS>TXCIE</ALIAS>
<DESCRIPTION>TX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRIE0</NAME>
<ALIAS>UDRIE</ALIAS>
<DESCRIPTION>USART Data register Empty Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RXEN0</NAME>
<ALIAS>RXEN</ALIAS>
<DESCRIPTION>Receiver Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TXEN0</NAME>
<ALIAS>TXEN</ALIAS>
<DESCRIPTION>Transmitter Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ02</NAME>
<ALIAS>UCSZ2</ALIAS>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>RXB80</NAME>
<ALIAS>RXB8</ALIAS>
<DESCRIPTION>Receive Data Bit 8</DESCRIPTION>
<TEXT>RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TXB80</NAME>
<ALIAS>TXB8</ALIAS>
<DESCRIPTION>Transmit Data Bit 8</DESCRIPTION>
<TEXT>TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.</TEXT>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR0B>
<UCSR0C>
<NAME>UCSR0C</NAME>
<ALIAS>UBRRHI</ALIAS>
<DESCRIPTION>USART Control and Status Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>URSEL0</NAME>
<DESCRIPTION>Register Select</DESCRIPTION>
<TEXT>This bit selects between accessing the UCSRC or the UBRRH register.It is read as one when reading UCSRC.The URSEL must be one when writing the UCSRC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UMSEL0</NAME>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT>0: Asynchronous Operation. 1: Synchronous Operation</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UPM01</NAME>
<DESCRIPTION>Parity Mode Bit 1</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UPM00</NAME>
<DESCRIPTION>Parity Mode Bit 0</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USBS0</NAME>
<DESCRIPTION>Stop Bit Select</DESCRIPTION>
<TEXT>0: 1-bit. 1: 2-bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ01</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UCSZ00</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UCPOL0</NAME>
<DESCRIPTION>Clock Polarity</DESCRIPTION>
<TEXT>This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR0C>
<UBRR0H>
<NAME>UBRR0H</NAME>
<DESCRIPTION>USART Baud Rate Register Hight Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>URSEL</NAME>
<DESCRIPTION>Register Select</DESCRIPTION>
<TEXT>This bit selects between accessing the UCSRC or the UBRRH register.It is read as one when reading UCSRC.The URSEL must be one when writing the UCSRC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT3>
<NAME>UBRR11</NAME>
<DESCRIPTION>USART Baud Rate Register bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR10</NAME>
<DESCRIPTION>USART Baud Rate Register bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR9</NAME>
<DESCRIPTION>USART Baud Rate Register bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR8</NAME>
<DESCRIPTION>USART Baud Rate Register bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR0H>
<UBRR0L>
<NAME>UBRR0L</NAME>
<ALIAS>UBRR0</ALIAS>
<ALIAS>UBRR</ALIAS>
<DESCRIPTION>USART Baud Rate Register Low Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>$09</IO_ADDR>
<MEM_ADDR>$29</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UBRR7</NAME>
<DESCRIPTION>USART Baud Rate Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UBRR6</NAME>
<DESCRIPTION>USART Baud Rate Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UBRR5</NAME>
<DESCRIPTION>USART Baud Rate Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UBRR4</NAME>
<DESCRIPTION>USART Baud Rate Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UBRR3</NAME>
<DESCRIPTION>USART Baud Rate Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR2</NAME>
<DESCRIPTION>USART Baud Rate Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR1</NAME>
<DESCRIPTION>USART Baud Rate Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR0</NAME>
<DESCRIPTION>USART Baud Rate Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR0L>
</USART0>
<USART1>
<LIST>[UDR1:UCSR1A:UCSR1B:UCSR1C:UBRR1H:UBRR1L]</LIST>
<LINK>[UBRR1H:UBRR1L]</LINK>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communicat</TEXT>
<UDR1>
<NAME>UDR</NAME>
<DESCRIPTION>USART I/O Data Register</DESCRIPTION>
<TEXT>The UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.</TEXT>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UDR1-7</NAME>
<DESCRIPTION>USART1 I/O Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UDR1-6</NAME>
<DESCRIPTION>USART1 I/O Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDR1-5</NAME>
<DESCRIPTION>USART1 I/O Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UDR1-4</NAME>
<DESCRIPTION>USART1 I/O Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UDR1-3</NAME>
<DESCRIPTION>USART1 I/O Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UDR1-2</NAME>
<DESCRIPTION>USART1 I/O Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UDR1-1</NAME>
<DESCRIPTION>USART1 I/O Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UDR1-0</NAME>
<DESCRIPTION>USART1 I/O Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UDR1>
<UCSR1A>
<NAME>UCSR1A</NAME>
<DESCRIPTION>USART Control and Status Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>$02</IO_ADDR>
<MEM_ADDR>$22</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXC1</NAME>
<DESCRIPTION>USART Receive Complete</DESCRIPTION>
<TEXT>This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXC1</NAME>
<DESCRIPTION>USART Transmitt Complete</DESCRIPTION>
<TEXT>This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRE1</NAME>
<DESCRIPTION>USART Data Register Empty</DESCRIPTION>
<TEXT>This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>FE1</NAME>
<DESCRIPTION>Framing Error</DESCRIPTION>
<TEXT>This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DOR1</NAME>
<DESCRIPTION>Data overRun</DESCRIPTION>
<TEXT>This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. </TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UPE1</NAME>
<DESCRIPTION>Parity Error</DESCRIPTION>
<TEXT>This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>U2X1</NAME>
<DESCRIPTION>Double the USART transmission speed</DESCRIPTION>
<TEXT>This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MPCM1</NAME>
<DESCRIPTION>Multi-processor Communication Mode</DESCRIPTION>
<TEXT>This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR1A>
<UCSR1B>
<NAME>UCSR1B</NAME>
<DESCRIPTION>USART Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$01</IO_ADDR>
<MEM_ADDR>$21</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXCIE1</NAME>
<DESCRIPTION>RX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXCIE1</NAME>
<DESCRIPTION>TX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRIE1</NAME>
<DESCRIPTION>USART Data register Empty Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RXEN1</NAME>
<DESCRIPTION>Receiver Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TXEN1</NAME>
<DESCRIPTION>Transmitter Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ12</NAME>
<ALIAS>CHR91</ALIAS>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR1C sets the number of data bits (character size) in a frame the receiver and transmitter use.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>RXB81</NAME>
<DESCRIPTION>Receive Data Bit 8</DESCRIPTION>
<TEXT>RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TXB81</NAME>
<DESCRIPTION>Transmit Data Bit 8</DESCRIPTION>
<TEXT>TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.</TEXT>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR1B>
<UCSR1C>
<NAME>UCSR1C</NAME>
<DESCRIPTION>USART Control and Status Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3C</IO_ADDR>
<MEM_ADDR>$5C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>URSEL1</NAME>
<DESCRIPTION>Register Select</DESCRIPTION>
<TEXT>This bit selects between accessing the UCSRC or the UBRRH register.It is read as one when reading UCSRC.The URSELmust be one when writing the UCSRC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UMSEL1</NAME>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT>0: Asynchronous Operation. 1: Synchronous Operation</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UPM11</NAME>
<DESCRIPTION>Parity Mode Bit 1</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UPM10</NAME>
<DESCRIPTION>Parity Mode Bit 0</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USBS1</NAME>
<DESCRIPTION>Stop Bit Select</DESCRIPTION>
<TEXT>0: 1-bit. 1: 2-bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ11</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UCSZ10</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UCPOL1</NAME>
<DESCRIPTION>Clock Polarity</DESCRIPTION>
<TEXT>This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR1C>
<UBRR1H>
<NAME>UBRR1H</NAME>
<DESCRIPTION>USART Baud Rate Register Highg Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR1H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>$3C</IO_ADDR>
<MEM_ADDR>$5C</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>UBRR11</NAME>
<DESCRIPTION>USART Baud Rate Register bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR10</NAME>
<DESCRIPTION>USART Baud Rate Register bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR9</NAME>
<DESCRIPTION>USART Baud Rate Register bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR8</NAME>
<DESCRIPTION>USART Baud Rate Register bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR1H>
<UBRR1L>
<NAME>UBRR1L</NAME>
<ALIAS>UBRR1</ALIAS>
<DESCRIPTION>USART Baud Rate Register Low Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>$00</IO_ADDR>
<MEM_ADDR>$20</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UBRR1L7</NAME>
<DESCRIPTION>USART Baud Rate Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UBRR1L6</NAME>
<DESCRIPTION>USART Baud Rate Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UBRR1L5</NAME>
<DESCRIPTION>USART Baud Rate Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UBRR1L4</NAME>
<DESCRIPTION>USART Baud Rate Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UBRR1L3</NAME>
<DESCRIPTION>USART Baud Rate Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR1L2</NAME>
<DESCRIPTION>USART Baud Rate Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR1L1</NAME>
<DESCRIPTION>USART Baud Rate Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR1L0</NAME>
<DESCRIPTION>USART Baud Rate Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR1L>
</USART1>
<TIMER_COUNTER_2>
<LIST>[TCCR2:TCNT2:OCR2:TIMSK:TIFR:ASSR]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>t8pwm1_01</ID>
<TEXT/>
<TCCR2>
<NAME>TCCR2</NAME>
<DESCRIPTION>Timer/Counter Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC2</NAME>
<DESCRIPTION>Forde Output Compare</DESCRIPTION>
<TEXT>The FOC2 bit is only active when the WGM bits specify a non-PWM mode.However,for ensuring compatibility with future devices,this bit must be set to zero when TCCR2 is written when operating in PWM mode.When writing a logical one to the FOC2 bit,an immediate compare match is forced on the waveform generation unit.The OC2 output is changed according to its COM21:0 bits setting.Note that the FOC2 bit is implemented as a strobe.Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. </TEXT>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WGM20</NAME>
<ALIAS>PWM2</ALIAS>
<DESCRIPTION>Pulse Width Modulator Select Bit 0</DESCRIPTION>
<TEXT>These bits control the counting sequence of the counter,the source for the maximum (TOP)counter value,and what type of waveform generation to be used.Modes of oper-ation supported by the Timer/Counter unit are:Normal mode,Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM21</NAME>
<DESCRIPTION>Compare Match Output Mode</DESCRIPTION>
<TEXT>These bits control the output compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 64 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM20</NAME>
<DESCRIPTION>Compare Match Output Mode</DESCRIPTION>
<TEXT>These bits control the output compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 64 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PW</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WGM21</NAME>
<ALIAS>CTC2</ALIAS>
<DESCRIPTION>Pulse Width Modulator Select Bit 1</DESCRIPTION>
<TEXT>These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS22</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT>The three clock select bits select the clock source to be used by the Timer/Counter.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS21</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT>The three clock select bits select the clock source to be used by the Timer/Counter.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS20</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT>The three clock select bits select the clock source to be used by the Timer/Counter.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR2>
<TCNT2>
<NAME>TCNT2</NAME>
<DESCRIPTION>Timer/Counter Register</DESCRIPTION>
<TEXT>The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a compare match between TCNT2 the OCR2 register. </TEXT>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT2_7</NAME>
<DESCRIPTION>Timer/Counter Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT2_6</NAME>
<DESCRIPTION>Timer/Counter Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT2_5</NAME>
<DESCRIPTION>Timer/Counter Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT2_4</NAME>
<DESCRIPTION>Timer/Counter Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT2_3</NAME>
<DESCRIPTION>Timer/Counter Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT2_2</NAME>
<DESCRIPTION>Timer/Counter Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT2_1</NAME>
<DESCRIPTION>Timer/Counter Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT2_0</NAME>
<DESCRIPTION>Timer/Counter Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT2>
<OCR2>
<NAME>OCR2</NAME>
<DESCRIPTION>Output Compare Register</DESCRIPTION>
<TEXT>The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin.</TEXT>
<IO_ADDR>$22</IO_ADDR>
<MEM_ADDR>$42</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR2_7</NAME>
<DESCRIPTION>Output Compare Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR2_6</NAME>
<DESCRIPTION>Output Compare Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR2_5</NAME>
<DESCRIPTION>Output Compare Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR2_4</NAME>
<DESCRIPTION>Output Compare Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR2_3</NAME>
<DESCRIPTION>Output Compare Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2_2</NAME>
<DESCRIPTION>Output Compare Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2_1</NAME>
<DESCRIPTION>Output Compare Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2_0</NAME>
<DESCRIPTION>Output Compare Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2>
<TIMSK>
<NAME>TIMSK</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>OCIE2</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match inter-rupt is enabled. The corresponding interrupt (at vector $003) is executed if a compare match in Timer/Counter2 occurs (i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT2>
<NAME>TOIE2</NAME>
<DESCRIPTION>Timer/Counter2 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
</TIMSK>
<TIFR>
<NAME>TIFR</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>OCF2</NAME>
<DESCRIPTION>Output Compare Flag 2</DESCRIPTION>
<TEXT>The OCF2 bit is set (one)when a compare match occurs between the Timer/Counter2 and the data in OCR2 -Output Compare Register2.OCF2 is cleared by hardware when executing the corresponding interrupt handling vector.Alternatively,OCF2 is cleared by writing a logic one to the flag.When the I-bit in SREG,OCIE2 (Timer/Counter2 Compare match Interrupt Enable),and OCF2 are set (one),the Timer/Counter2 Compare match Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT2>
<NAME>TOV2</NAME>
<DESCRIPTION>Timer/Counter2 Overflow Flag </DESCRIPTION>
<TEXT>The TOV2 bit is set (one)when an overflow occurs in Timer/Counter2.TOV2 is cleared by hardware when executing the corresponding interrupt handling vector.Alternatively, TOV2 is cleared by writing a logic one to the flag.When the SREG I-bit,TOIE2 (Timer/Counter2 Overflow Interrupt Enable),and TOV2 are set (one),the Timer/Counter2 Overflow interrupt is executed.In PWM mode,this bit is set when Timer/Counter2 changes counting direction at $00. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
</TIFR>
<ASSR>
<NAME>ASSR</NAME>
<DESCRIPTION>Asynchronous Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>AS2</NAME>
<DESCRIPTION>Asynchronous Timer 2</DESCRIPTION>
<TEXT>When AS2 is set (one), Timer/Counter2 is clocked from the TOSC1 pin. Pins PC6 and PC7 become connected to a crystal oscillator and cannot be used as general I/O pins. When cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When the value of this bit is changed, the contents of TCNT2, OCR2 and TCCR2 might get corrupted.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCN2UB</NAME>
<DESCRIPTION>Timer/Counter2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that TCNT2 is ready to be updated with a new value.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2UB</NAME>
<DESCRIPTION>Output Compare Register2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that OCR2 is ready to be updated with a new value.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCR2UB</NAME>
<DESCRIPTION>Timer/Counter Control Register2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 registers while its Update Busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2 and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is rea</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ASSR>
</TIMER_COUNTER_2>
<ANALOG_COMPARATOR>
<LIST>[ACSR]</LIST>
<LINK/>
<ICON>io_analo.bmp</ICON>
<ID>AlgComp_01</ID>
<TEXT/>
<ACSR>
<NAME>ACSR</NAME>
<DESCRIPTION>Analog Comparator Control And Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ACD</NAME>
<DESCRIPTION>Analog Comparator Disable</DESCRIPTION>
<TEXT>When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ACBG</NAME>
<ALIAS>AINBG</ALIAS>
<DESCRIPTION>Analog Comparator Bandgap Select</DESCRIPTION>
<TEXT>When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ACO</NAME>
<DESCRIPTION>Analog Compare Output</DESCRIPTION>
<TEXT>The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>NA</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ACI</NAME>
<DESCRIPTION>Analog Comparator Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ACIE</NAME>
<DESCRIPTION>Analog Comparator Interrupt Enable</DESCRIPTION>
<TEXT>When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ACIC</NAME>
<DESCRIPTION>Analog Comparator Input Capture Enable</DESCRIPTION>
<TEXT>When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ACIS1</NAME>
<DESCRIPTION>Analog Comparator Interrupt Mode Select bit 1</DESCRIPTION>
<TEXT>These bits determine which comparator events that trigger the Analog Comparator interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ACIS0</NAME>
<DESCRIPTION>Analog Comparator Interrupt Mode Select bit 0</DESCRIPTION>
<TEXT>These bits determine which comparator events that trigger the Analog Comparator interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ACSR>
</ANALOG_COMPARATOR>
<CPU>
<LIST>[SREG:SPH:SPL:MCUCR:MCUCSR:EMCUCR:OSCCAL:CLKPR:SFIOR]</LIST>
<LINK>[SPH:SPL]</LINK>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT/>
<SREG>
<NAME>SREG</NAME>
<DESCRIPTION>Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>I</NAME>
<DESCRIPTION>Global Interrupt Enable</DESCRIPTION>
<TEXT>The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>T</NAME>
<DESCRIPTION>Bit Copy Storage</DESCRIPTION>
<TEXT>The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>H</NAME>
<DESCRIPTION>Half Carry Flag</DESCRIPTION>
<TEXT>The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>S</NAME>
<DESCRIPTION>Sign Bit</DESCRIPTION>
<TEXT>The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>V</NAME>
<DESCRIPTION>Two's Complement Overflow Flag</DESCRIPTION>
<TEXT>The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>N</NAME>
<DESCRIPTION>Negative Flag</DESCRIPTION>
<TEXT>The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>Z</NAME>
<DESCRIPTION>Zero Flag</DESCRIPTION>
<TEXT>The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>C</NAME>
<DESCRIPTION>Carry Flag</DESCRIPTION>
<TEXT>The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SREG>
<SPH>
<NAME>SPH</NAME>
<DESCRIPTION>Stack Pointer High</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R</TEXT>
<IO_ADDR>$3E</IO_ADDR>
<MEM_ADDR>$5E</MEM_ADDR>
<ICON>io_sph.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP15</NAME>
<DESCRIPTION>Stack pointer bit 15</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP14</NAME>
<DESCRIPTION>Stack pointer bit 14</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP13</NAME>
<DESCRIPTION>Stack pointer bit 13</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP12</NAME>
<DECRIPTION>Stack pointer bit 12</DECRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP11</NAME>
<DESCRIPTION>Stack pointer bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP10</NAME>
<DESCRIPTION>Stack pointer bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP9</NAME>
<DESCRIPTION>Stack pointer bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP8</NAME>
<DESCRIPTION>Stack pointer bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPH>
<SPL>
<NAME>SPL</NAME>
<DESCRIPTION>Stack Pointer Low</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt </TEXT>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<ICON>io_sph.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP7</NAME>
<DESCRIPTION>Stack pointer bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP6</NAME>
<DESCRIPTION>Stack pointer bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP5</NAME>
<DESCRIPTION>Stack pointer bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP4</NAME>
<DECRIPTION>Stack pointer bit 4</DECRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP3</NAME>
<DESCRIPTION>Stack pointer bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP2</NAME>
<DESCRIPTION>Stack pointer bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP1</NAME>
<DESCRIPTION>Stack pointer bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP0</NAME>
<DESCRIPTION>Stack pointer bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPL>
<MCUCR>
<NAME>MCUCR</NAME>
<DESCRIPTION>MCU Control Register</DESCRIPTION>
<TEXT>The MCU Control Register contains control bits for general MCU functions.</TEXT>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SRE</NAME>
<DESCRIPTION>External SRAM Enable</DESCRIPTION>
<TEXT>Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are acti-vated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction regis-ters. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SRW10</NAME>
<ALIAS>SRW</ALIAS>
<DESCRIPTION>External SRAM Wait State Select</DESCRIPTION>
<TEXT>For a detailed description in non ATmega103 Compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 Compatibility mode, writing SRW10 to one enables the wait state and one extra cycle is added during read/write strobe as shown in Figure 14.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SE</NAME>
<DESCRIPTION>Sleep Enable</DESCRIPTION>
<TEXT>The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To avoid the MCU entering the sleep mode unless it is the programmers purpose,it is recommended to write the Sleep Enable (SE)bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SM1</NAME>
<ALIAS>SM</ALIAS>
<DESCRIPTION>Sleep Mode Select</DESCRIPTION>
<TEXT>The description is to long for the tooltip help, please refer to the manual</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ISC11</NAME>
<DESCRIPTION>Interrupt Sense Control 1 bit 1</DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corresponding interrupt mask in the GICR are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ISC10</NAME>
<DESCRIPTION>Interrupt Sense Control 1 bit 1</DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corresponding interrupt mask in the GICR are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ISC01</NAME>
<DESCRIPTION>Interrupt Sense Control 0 bit 1</DESCRIPTION>
<TEXT>The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC00</NAME>
<DESCRIPTION>Interrupt Sense Control 0 bit 0</DESCRIPTION>
<TEXT>The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUCR>
<MCUCSR>
<NAME>MCUCSR</NAME>
<ALIAS>MCUSR</ALIAS>
<DESCRIPTION>MCU Control And Status Register</DESCRIPTION>
<TEXT>The MCU Control And Status Register provides information on which reset source caused a MCU reset.</TEXT>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>JDT</NAME>
<DESCRIPTION>JTAG Interface Disable</DESCRIPTION>
<TEXT>When this bit is zero,the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is one,the JTAG interface is disabled.In order to avoid unintentional disabling or enabling of the JTAG interface,a timed sequence must be followed when changing this bit:The application software must write this bit to the desired value twice within four cycles to change its value. </TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT5>
<NAME>SM2</NAME>
<DESCRIPTION>Sleep Mode Select Bit 2</DESCRIPTION>
<TEXT>The Sleep Mode Select bits select between the five available sleep modes. See Datasheet.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>JTRF</NAME>
<DESCRIPTION>JTAG Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. • Bit 3 - WDRF: Watchdog Reset Flag</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WDRF</NAME>
<DESCRIPTION>Watchdog Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>BORF</NAME>
<DESCRIPTION>Brown-out Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EXTRF</NAME>
<DESCRIPTION>External Reset Flag</DESCRIPTION>
<TEXT>This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORF</NAME>
<DESCRIPTION>Power-on reset flag</DESCRIPTION>
<TEXT>This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUCSR>
<EMCUCR>
<NAME>EMCUCR</NAME>
<DESCRIPTION>Extended MCU Control Register</DESCRIPTION>
<TEXT>The Extended MCU Control Register contains control bits for general MCU functions.</TEXT>
<IO_ADDR>$36</IO_ADDR>
<MEM_ADDR>$56</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SM0</NAME>
<DESCRIPTION>Sleep mode Select Bit 0</DESCRIPTION>
<TEXT>The Sleep Mode Select bits select between the five available sleep modes. See Datasheet. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SRL2</NAME>
<DESCRIPTION>Wait State Sector Limit Bit 2</DESCRIPTION>
<TEXT>It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits.The SRL2,SRL1,and SRL0 bits select the splitting of these sectors. By default,the SRL2,SRL1,and SRL0 bits are set to zero and the entire external memory address space is treated as one sector.When the entire SRAM address space is configured as one sector,the wait-states are configured by the SRW11 and SRW10 bits. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SRL1</NAME>
<DESCRIPTION>Wait State Sector Limit Bit 1</DESCRIPTION>
<TEXT>It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits.The SRL2,SRL1,and SRL0 bits select the splitting of these sectors. By default,the SRL2,SRL1,and SRL0 bits are set to zero and the entire external memory address space is treated as one sector.When the entire SRAM address space is configured as one sector,the wait-states are configured by the SRW11 and SRW10 bits. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SRL0</NAME>
<DESCRIPTION>Wait State Sector Limit Bit 0</DESCRIPTION>
<TEXT>It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits.The SRL2,SRL1,and SRL0 bits select the splitting of these sectors. By default,the SRL2,SRL1,and SRL0 bits are set to zero and the entire external memory address space is treated as one sector.When the entire SRAM address space is configured as one sector,the wait-states are configured by the SRW11 and SRW10 bits. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SRW01</NAME>
<DESCRIPTION>Wait State Select Bit 1 for Lower Sector</DESCRIPTION>
<TEXT>The SRW00 and SRW01 bits control the number of wait-states for the upper sector of the external memory address space. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SRW00</NAME>
<DESCRIPTION>Wait State Select Bit 0 for Lower Sector</DESCRIPTION>
<TEXT>The SRW00 and SRW01 bits control the number of wait-states for the upper sector of the external memory address space. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SRW11</NAME>
<DESCRIPTION>Wait State Select Bit 1 for Upper Sector</DESCRIPTION>
<TEXT>The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the external memory address space. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC2</NAME>
<DESCRIPTION>Interrupt Sense Control 2</DESCRIPTION>
<TEXT>The asynchronous external interrupt 2 is activated by the external pin INT2 if the SREG I-bit and the corresponding interrupt mask in GICR are set.If ISC2 is written to zero,a falling edge on INT2 activates the interrupt.If ISC2 is written to one,a rising edge on INT2 activates the interrupt.Edges on INT2 are registered asynchronously.Pulses on INT2 wider than the minimum pulse given width will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.When changing the ISC2 bit,an interrupt can occur.Therefore,it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR register.Then,the ISC2 bit can be changed.Finally, the INT2 interruptflag should becleared by writing a logical one to its Interrupt Flagbit (INTF2)in the GIFR register before the interrupt is re-enabled. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EMCUCR>
<OSCCAL>
<NAME>OSCCAL</NAME>
<DESCRIPTION>Oscillator Calibration Value</DESCRIPTION>
<TEXT>Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 1</TEXT>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT6>
<NAME>CAL6</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit6</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CAL5</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit5</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CAL4</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit4</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CAL3</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit3</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CAL2</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit2</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CAL1</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit1</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CAL0</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit0</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OSCCAL>
<CLKPR>
<NAME>CLKPR</NAME>
<DESCRIPTION>Clock prescale register</DESCRIPTION>
<TEXT>The ATmega162 system clock can be divided by setting the Clock Prescale Register CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$61</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>CLKPCE</NAME>
<DESCRIPTION>Clock Prescaler Change Enable</DESCRIPTION>
<TEXT>The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS is written.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT3>
<NAME>CLKPS3</NAME>
<DESCRIPTION>Clock Prescaler Select Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CLKPS2</NAME>
<DESCRIPTION>Clock Prescaler Select Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CLKPS1</NAME>
<DESCRIPTION>Clock Prescaler Select Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CLKPS0</NAME>
<DESCRIPTION>Clock Prescaler Select Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CLKPR>
<SFIOR>
<NAME>SFIOR</NAME>
<DESCRIPTION>Special Function IO Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TSM</NAME>
<DESCRIPTION>Timer/Counter Synchronization Mode</DESCRIPTION>
<TEXT>Writing TSM to one,PSR0 and PSR321 becomes registers that hold their value until rewritten,or the TSM bit is written zero.This mode is useful for synchronizing timer/counters.By setting both TSM and the appropriate PSR bit(s),the appropriate timer/counters are halted,and can be configured to same value without the risk of one of them advancing during configuration.When the TSM bit is written zero,the Timer/Counters start counting simultaneously.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>XMBK</NAME>
<DESCRIPTION>External Memory Bus Keeper Enable</DESCRIPTION>
<TEXT>Writing XMBK to one enables the bus keeper on the AD7:0 lines.When the bus keeper</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>XMM2</NAME>
<DESCRIPTION>External Memory High Mask Bit 2</DESCRIPTION>
<TEXT>Please refer to the datasheet for a full description of the usage.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>XMM1</NAME>
<DESCRIPTION>External Memory High Mask Bit 1</DESCRIPTION>
<TEXT>Please refer to the datasheet for a full description of the usage.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>XMM0</NAME>
<DESCRIPTION>External Memory High Mask Bit 0</DESCRIPTION>
<TEXT>Please refer to the datasheet for a full description of the usage.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PUD</NAME>
<DESCRIPTION>Pull-up Disable</DESCRIPTION>
<TEXT>When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PSR2</NAME>
<DESCRIPTION>Prescaler Reset Timer/Counter2</DESCRIPTION>
<TEXT>When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PSR310</NAME>
<ALIAS>PSR10</ALIAS>
<ALIAS>PSR0</ALIAS>
<ALIAS>PSR1</ALIAS>
<DESCRIPTION>Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0</DESCRIPTION>
<TEXT>When this bit is written to one,the Timer/Counter3,Timer/Counter1,and Timer/Counter0 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.Note that Timer/Counter3,Timer/Counter1,and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect all 3 timers.This bit will always be read as zero.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SFIOR>
</CPU>
<BOOT_LOAD>
<LIST>[SPMCR]</LIST>
<LINK/>
<RULES/>
<ICON>io_cpu.bmp</ICON>
<ID>00</ID>
<TEXT>The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppo</TEXT>
<SPMCR>
<NAME>SPMCR</NAME>
<DESCRIPTION>Store Program Memory Control Register</DESCRIPTION>
<TEXT>The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.</TEXT>
<IO_ADDR>$37</IO_ADDR>
<MEM_ADDR>$57</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPMIE</NAME>
<DESCRIPTION>SPM Interrupt Enable</DESCRIPTION>
<TEXT>When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>RWWSB</NAME>
<ALIAS>ASB</ALIAS>
<DESCRIPTION>Read While Write Section Busy</DESCRIPTION>
<TEXT>When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT4>
<NAME>RWWSRE</NAME>
<ALIAS>ASRE</ALIAS>
<DESCRIPTION>Read While Write secion read enable</DESCRIPTION>
<TEXT>When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>BLBSET</NAME>
<DESCRIPTION>Boot Lock Bit Set</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for details</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PGWRT</NAME>
<DESCRIPTION>Page Write</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PGERS</NAME>
<DESCRIPTION>Page Erase</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPMEN</NAME>
<DESCRIPTION>Store Program Memory Enable</DESCRIPTION>
<TEXT>This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPMCR>
</BOOT_LOAD>
<EXTERNAL_INTERRUPT>
<LIST>[MCUCR:EMCUCR:GICR:GIFR:PCMSK1:PCMSK0]</LIST>
<LINK/>
<ICON>io_ext.bmp</ICON>
<ID/>
<TEXT/>
<MCUCR>
<NAME>MCUCR</NAME>
<DESCRIPTION>MCU Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>ISC11</NAME>
<DESCRIPTION>Interrupt Sense Control 1 Bit 1</DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I bit and the corresponding interrupt mask in the GICR are set.The level and edges on the external INT1 pin that activate the interrupt are defined below.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC11:ISC10) Description: (0:0) The low level of INT1 generates an interrupt request. (0:1) Any logical change on INT1 generates an interrupt request. (1:0) The falling edge of INT1 generates an interrupt request. (1:1) The rising edge of INT1 generates an interrupt reques</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ISC10</NAME>
<DESCRIPTION>Interrupt Sense Control 1 Bit 0</DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I bit and the corresponding interrupt mask in the GICR are set.The level and edges on the external INT1 pin that activate the interrupt are defined below.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC11:ISC10) Description: (0:0) The low level of INT1 generates an interrupt request. (0:1) Any logical change on INT1 generates an interrupt request. (1:0) The falling edge of INT1 generates an interrupt request. (1:1) The rising edge of INT1 generates an interrupt reques</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ISC01</NAME>
<DESCRIPTION>Interrupt Sense Control 0 Bit 1</DESCRIPTION>
<TEXT>The External Interrupt 0 is activated by the external pin INT0 if the SREG I flag and the corresponding interrupt mask are set.The level and edges on the external INT0 pin that activate the interrupt are defined below. The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC01:ISC00) Description: (0:0) The low level of INT0 generates an interrupt request. (0:1) Any logical change on INT0 generates an interrupt request. (1:0) The falling edge of INT0 generates an interrupt request. (1:1) The rising edge of INT0 generates an interrupt request</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC00</NAME>
<DESCRIPTION>Interrupt Sense Control 0 Bit 0</DESCRIPTION>
<TEXT>The External Interrupt 0 is activated by the external pin INT0 if the SREG I flag and the corresponding interrupt mask are set.The level and edges on the external INT0 pin that activate the interrupt are defined below. The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC01:ISC00) Description: (0:0) The low level of INT0 generates an interrupt request. (0:1) Any logical change on INT0 generates an interrupt request. (1:0) The falling edge of INT0 generates an interrupt request. (1:1) The rising edge of INT0 generates an interrupt request</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUCR>
<EMCUCR>
<NAME>EMCUCR</NAME>
<DESCRIPTION>Extended MCU Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$36</IO_ADDR>
<MEM_ADDR>$56</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT0>
<NAME>ISC2</NAME>
<DESCRIPTION>Interrupt Sense Control 2</DESCRIPTION>
<TEXT>The asynchronous external interrupt 2 is activated by the external pin INT2 if the SREG I-bit and the corresponding interrupt mask in GICR are set.If ISC2 is written to zero,a falling edge on INT2 activates the interrupt.If ISC2 is written to one,a rising edge on INT2 activates the interrupt.Edges on INT2 are registered asynchronously.Pulses on INT2 wider than the minimum pulse width given in Table 41 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.When changing the ISC2 bit,an interrupt can occur.Therefore,it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR register.Then,the ISC2 bit can be changed.Finally, the INT2 interruptflag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2)in the GIFR register before the interrupt is re-enabled. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EMCUCR>
<GICR>
<NAME>GICR</NAME>
<ALIAS>EIMSK</ALIAS>
<ALIAS>GIMSK</ALIAS>
<DESCRIPTION>General Interrupt Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3B</IO_ADDR>
<MEM_ADDR>$5B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>INT1</NAME>
<DESCRIPTION>External Interrupt Request 1 Enable</DESCRIPTION>
<TEXT>When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>INT0</NAME>
<DESCRIPTION>External Interrupt Request 0 Enable</DESCRIPTION>
<TEXT>When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>INT2</NAME>
<DESCRIPTION>External Interrupt Request 2 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PCIE1</NAME>
<DESCRIPTION>Pin Change Interrupt Enable 1</DESCRIPTION>
<TEXT>When the PCIE1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one), pin change interrupt 1 is enabled.Any change on any enabled PCINT15..8 pin will cause an interrupt.The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 interrupt vector.PCINT15..8 pins are enabled individually by the PCMSK1 register. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PCIE0</NAME>
<DESCRIPTION>Pin Change Interrupt Enable 0</DESCRIPTION>
<TEXT>When the PCIE0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT1>
<NAME>IVSEL</NAME>
<DESCRIPTION>Interrupt Vector Select</DESCRIPTION>
<TEXT>When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses.Refer to the section “Boot Loader Support Read While Write self-programming ”on page 203 for details.To avoid unintentional changes of interrupt vector tables,a special write procedure must be followed to change the IVSEL bit: 1.Write the Interrupt Vector Change Enable (IVCE)bit to one. 2.Within four cycles,write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed.Interrupts are disabled in the cycle IVCE is set,and they remain disabled until after the instruction following the write to IVSEL.If IVSEL is not written,interrupts remain disabled for four cycles.The I-bit in the Status Register is unaffected by the automatic disabling. Note:If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,interrupts are disabled while executing from the Application section.If interrupt vectors are placed in the Application section and Boot Lock bit BLB12 is programed,interrupts are disabled while executing from the Boot Loader section.Refer to the section “Boot Loader Support -Read While Write self-programming ”on page 203 for details on Boot Lock bits</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>IVCE</NAME>
<DESCRIPTION>Interrupt Vector Change Enable</DESCRIPTION>
<TEXT>The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GICR>
<GIFR>
<NAME>GIFR</NAME>
<DESCRIPTION>General Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3A</IO_ADDR>
<MEM_ADDR>$5A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>INTF1</NAME>
<DESCRIPTION>External Interrupt Flag 1</DESCRIPTION>
<TEXT>When an event on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I bit in SREG and the INT1 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT1 is configured as a level interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>INTF0</NAME>
<DESCRIPTION>External Interrupt Flag 0</DESCRIPTION>
<TEXT>When an event on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I bit in SREG and the INT0 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt rou tine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>INTF2</NAME>
<DESCRIPTION>External Interrupt Flag 2</DESCRIPTION>
<TEXT>When an event on the INT2 pin triggers an interrupt request,INTF2 becomes set (one).If the I bit in SREG and the INT2 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt rou tine is executed.Alternatively,the flag can be cleared by writing a logical one to it.Note that when entering some sleep modes with the INT2 interrupt disabled,the input buffer on this pin will be disabled.This may cause a logic change in inter nal signals which will set the INTF2 flag</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PCIF1</NAME>
<DESCRIPTION>Pin Change Interrupt Flag 1</DESCRIPTION>
<TEXT>When a logic change on any PCINT15..8 pin triggers an interrupt request,PCIF1 becomes set (one).If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PCIF0</NAME>
<DESCRIPTION>Pin Change Interrupt Flag 0</DESCRIPTION>
<TEXT>When a logic change on any PCINT7..0 pin triggers an interrupt request,PCIF0 becomes set (one).If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
</GIFR>
<PCMSK1>
<NAME>PCMSK1</NAME>
<DESCRIPTION>Pin Change Mask Register 1</DESCRIPTION>
<TEXT>Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is set and the PCIE1 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is cleared,pin change interrupt on the corresponding I/O pin is disabled. </TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PCINT15</NAME>
<DESCRIPTION>Pin Change Enable Mask 15</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PCINT14</NAME>
<DESCRIPTION>Pin Change Enable Mask 14</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PCINT13</NAME>
<DESCRIPTION>Pin Change Enable Mask 13</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PCINT12</NAME>
<DESCRIPTION>Pin Change Enable Mask 12</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PCINT11</NAME>
<DESCRIPTION>Pin Change Enable Mask 11</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PCINT10</NAME>
<DESCRIPTION>Pin Change Enable Mask 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCINT9</NAME>
<DESCRIPTION>Pin Change Enable Mask 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCINT8</NAME>
<DESCRIPTION>Pin Change Enable Mask 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCMSK1>
<PCMSK0>
<NAME>PCMSK0</NAME>
<DESCRIPTION>Pin Change Enable Mask </DESCRIPTION>
<TEXT>Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT7..0 is set and the PCIE0 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT7..0 is cleared,pin change interrupt on the corresponding I/O pin is disabled. </TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PCINT7</NAME>
<DESCRIPTION>Pin Change Enable Mask 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PCINT6</NAME>
<DESCRIPTION>Pin Change Enable Mask 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PCINT5</NAME>
<DESCRIPTION>Pin Change Enable Mask 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PCINT4</NAME>
<DESCRIPTION>Pin Change Enable Mask 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PCINT3</NAME>
<DESCRIPTION>Pin Change Enable Mask 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PCINT2</NAME>
<DESCRIPTION>Pin Change Enable Mask 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCINT1</NAME>
<DESCRIPTION>Pin Change Enable Mask 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCINT0</NAME>
<DESCRIPTION>Pin Change Enable Mask 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCMSK0>
</EXTERNAL_INTERRUPT>
</IO_MODULE><ICE_SETTINGS><MODULE_LIST>[ICE50]</MODULE_LIST><ICE50>
<MMU_ACCESS>
<MemTypeSram8Bit>0x05</MemTypeSram8Bit>
<MemTypeSram16Bit>0x0F</MemTypeSram16Bit>
<MemTypeSramShdw8Bit>0x0F</MemTypeSramShdw8Bit>
<MemTypeSramShdw16Bit>0x0F</MemTypeSramShdw16Bit>
<MemTypeEeprom>0x05</MemTypeEeprom>
<MemTypeProgram>0x05</MemTypeProgram>
<MemTypePrgEventBreak>0x05</MemTypePrgEventBreak>
<MemTypePrgEventTrigOut>0x05</MemTypePrgEventTrigOut>
<MemTypePrgEventTraceCtrl>0x05</MemTypePrgEventTraceCtrl>
<MemTypePrgEventComplex>0x05</MemTypePrgEventComplex>
<MemTypeSramEventLow>0x05</MemTypeSramEventLow>
<MemTypeSramEventHigh>0x05</MemTypeSramEventHigh>
<MemTypeEepromEvent>0x05</MemTypeEepromEvent>
<MemTypeRegisterEvent>0x0F</MemTypeRegisterEvent>
<MemTypeIoEvent>0x0F</MemTypeIoEvent>
<MemTypePreTrace>0x0F</MemTypePreTrace>
<MemTypeTrace>0x15</MemTypeTrace>
<MemTypeCoreShdw>0x14</MemTypeCoreShdw>
<MemTypeCoreMem>0x14</MemTypeCoreMem>
</MMU_ACCESS>
<MMU_NOXRAM>
<MemTypeSram8Bit>0x00000FFF</MemTypeSram8Bit>
<MemTypeSram16Bit>0x00000000</MemTypeSram16Bit>
<MemTypeSramShdw8Bit>0x00000000</MemTypeSramShdw8Bit>
<MemTypeSramShdw16Bit>0x00000000</MemTypeSramShdw16Bit>
<MemTypeEeprom>0x00000FFF</MemTypeEeprom>
<MemTypeProgram>0x0001FFFF</MemTypeProgram>
<MemTypePrgEventBreak>0x0000FFFF</MemTypePrgEventBreak>
<MemTypePrgEventTrigOut>0x0000FFFF</MemTypePrgEventTrigOut>
<MemTypePrgEventTraceCtrl>0x0000FFFF</MemTypePrgEventTraceCtrl>
<MemTypePrgEventComplex>0x0000FFFF</MemTypePrgEventComplex>
<MemTypeSramEventLow>0x0000FFFF</MemTypeSramEventLow>
<MemTypeSramEventHigh>0x0000FFFF</MemTypeSramEventHigh>
<MemTypeEepromEvent>0x00000FFF</MemTypeEepromEvent>
<MemTypeRegisterEvent>0x00000000</MemTypeRegisterEvent>
<MemTypeIoEvent>0x00000000</MemTypeIoEvent>
<MemTypePreTrace>0x00000000</MemTypePreTrace>
<MemTypeTrace>0x0023FFFF</MemTypeTrace>
<MemTypeCoreShdw>0x00000FFF</MemTypeCoreShdw>
<MemTypeCoreMem>0x000000FF</MemTypeCoreMem>
</MMU_NOXRAM>
<MMU_EMULATED>
<MemTypeSram8Bit>0x0000FFFF</MemTypeSram8Bit>
<MemTypeSram16Bit>0x00000000</MemTypeSram16Bit>
<MemTypeSramShdw8Bit>0x00000000</MemTypeSramShdw8Bit>
<MemTypeSramShdw16Bit>0x00000000</MemTypeSramShdw16Bit>
<MemTypeEeprom>0x00000FFF</MemTypeEeprom>
<MemTypeProgram>0x0001FFFF</MemTypeProgram>
<MemTypePrgEventBreak>0x0000FFFF</MemTypePrgEventBreak>
<MemTypePrgEventTrigOut>0x0000FFFF</MemTypePrgEventTrigOut>
<MemTypePrgEventTraceCtrl>0x0000FFFF</MemTypePrgEventTraceCtrl>
<MemTypePrgEventComplex>0x0000FFFF</MemTypePrgEventComplex>
<MemTypeSramEventLow>0x0000FFFF</MemTypeSramEventLow>
<MemTypeSramEventHigh>0x0000FFFF</MemTypeSramEventHigh>
<MemTypeEepromEvent>0x00000FFF</MemTypeEepromEvent>
<MemTypeRegisterEvent>0x00000000</MemTypeRegisterEvent>
<MemTypeIoEvent>0x00000000</MemTypeIoEvent>
<MemTypePreTrace>0x00000000</MemTypePreTrace>
<MemTypeTrace>0x0023FFFF</MemTypeTrace>
<MemTypeCoreShdw>0x00000FFF</MemTypeCoreShdw>
<MemTypeCoreMem>0x000000FF</MemTypeCoreMem>
</MMU_EMULATED>
<MMU_XRAMIF>
<MemTypeSram8Bit>0x00000FFF</MemTypeSram8Bit>
<MemTypeSram16Bit>0x00000000</MemTypeSram16Bit>
<MemTypeSramShdw8Bit>0x00000000</MemTypeSramShdw8Bit>
<MemTypeSramShdw16Bit>0x00000000</MemTypeSramShdw16Bit>
<MemTypeEeprom>0x00000FFF</MemTypeEeprom>
<MemTypeProgram>0x0001FFFF</MemTypeProgram>
<MemTypePrgEventBreak>0x0000FFFF</MemTypePrgEventBreak>
<MemTypePrgEventTrigOut>0x0000FFFF</MemTypePrgEventTrigOut>
<MemTypePrgEventTraceCtrl>0x0000FFFF</MemTypePrgEventTraceCtrl>
<MemTypePrgEventComplex>0x0000FFFF</MemTypePrgEventComplex>
<MemTypeSramEventLow>0x0000FFFF</MemTypeSramEventLow>
<MemTypeSramEventHigh>0x0000FFFF</MemTypeSramEventHigh>
<MemTypeEepromEvent>0x00000FFF</MemTypeEepromEvent>
<MemTypeRegisterEvent>0x00000000</MemTypeRegisterEvent>
<MemTypeIoEvent>0x00000000</MemTypeIoEvent>
<MemTypePreTrace>0x00000000</MemTypePreTrace>
<MemTypeTrace>0x0023FFFF</MemTypeTrace>
<MemTypeCoreShdw>0x00000FFF</MemTypeCoreShdw>
<MemTypeCoreMem>0x0000FFFF</MemTypeCoreMem>
</MMU_XRAMIF>
<DEFAULT_SETTINGS>
<HighFuse>0xF9</HighFuse>
<ExtendedFuse>0xef</ExtendedFuse>
<LowFuse>0xE1</LowFuse>
<Lockbit>0xff</Lockbit>
<ADDROSC>0x24</ADDROSC>
<VALOSC>0x67</VALOSC>
<BINFILE>ATmega162.bin</BINFILE>
<PARAM_MMU_DMEM_PARTION>0x02</PARAM_MMU_DMEM_PARTION>
<PARAM_MMU_MEMCFG>0x00</PARAM_MMU_MEMCFG>
<FREQUENCY>1000000</FREQUENCY>
<MAXFREQUENCY>16000000</MAXFREQUENCY>
<CLOCK>2 ; INTOSC = 1, INTRC=2;EXTCLK=4</CLOCK>
<TIMEROSC>1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 </TIMEROSC>
<XTAL2SOURCING>1 </XTAL2SOURCING>
<PARAM_AVR_RMR>0</PARAM_AVR_RMR>
<XRAMENABLE>0x00</XRAMENABLE>
<XRAMOTHER>0x01</XRAMOTHER>
<DIVCLOCK>1 </DIVCLOCK>
</DEFAULT_SETTINGS>
<SETTINGS>
<BOOTSIZE>
<OPT1>
<LFMASK>0x00000600</LFMASK>
<LFBITS>0x00000600</LFBITS>
<TEXT>Boot Size 128 Words, 2 pages, $1F80-$1FFF, Boot reset $1F80</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x00000600</LFMASK>
<LFBITS>0x00000400</LFBITS>
<TEXT>Boot Size 256 Words, 4 pages, $1F00-$1FFF, Boot reset $1F00</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x00000600</LFMASK>
<LFBITS>0x00000200</LFBITS>
<TEXT>Boot Size 512 Words, 8 pages, $1E00-$1FFF, Boot reset $1E00</TEXT>
</OPT3>
<OPT4>
<LFMASK>0x00000600</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>Boot Size 1024 Words, 16 pages, $1C00-$1FFF, Boot reset $1C00</TEXT>
</OPT4>
</BOOTSIZE>
<CLOCK>
<STARTUP>
<INTOSC>
<OPT1>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>258 CK, 4 ms </TEXT>
</OPT1>
<OPT2>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000010</LFBITS>
<TEXT>258 CK, 64 ms</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000020</LFBITS>
<TEXT>1K CK</TEXT>
</OPT3>
<OPT4>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000030</LFBITS>
<TEXT>1K CK, 4 ms</TEXT>
</OPT4>
<OPT5>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000001</LFBITS>
<TEXT>1K CK, 64 ms</TEXT>
</OPT5>
<OPT6>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000011</LFBITS>
<TEXT>16K CK</TEXT>
</OPT6>
<OPT7>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000021</LFBITS>
<TEXT>16K CK, 4 ms</TEXT>
</OPT7>
<OPT8>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000031</LFBITS>
<TEXT>16K CK, 64 ms</TEXT>
</OPT8>
</INTOSC>
<INTRC>
<OPT1>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>6 CK</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000010</LFBITS>
<TEXT>6 CK, 4 ms</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000020</LFBITS>
<TEXT>6 CK, 64 ms</TEXT>
</OPT3>
</INTRC>
<EXTCLK>
<OPT1>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>6 CK</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000010</LFBITS>
<TEXT>6 CK, 4 ms</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000020</LFBITS>
<TEXT>6 CK, 64 ms</TEXT>
</OPT3>
</EXTCLK>
</STARTUP>
<CLOCK>
<INTOSC>
<LFMASK>0x0000003f</LFMASK>
<LFBITS>0x0000002b</LFBITS>
</INTOSC>
<INTRC>
<OPT1>
<LFMASK>0x0000003f</LFMASK>
<LFBITS>0x00000021</LFBITS>
<TEXT>1.0</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x0000003f</LFMASK>
<LFBITS>0x00000022</LFBITS>
<TEXT>2.0</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x0000003f</LFMASK>
<LFBITS>0x00000023</LFBITS>
<TEXT>4.0</TEXT>
</OPT3>
<OPT4>
<LFMASK>0x0000003f</LFMASK>
<LFBITS>0x00000024</LFBITS>
<TEXT>8.0</TEXT>
</OPT4>
</INTRC>
<EXTCLK>
<LFMASK>0x0000000f</LFMASK>
<LFBITS>0x00000000</LFBITS>
</EXTCLK>
</CLOCK>
</CLOCK>
<BOOTRESET>
<OPT1>
<LFMASK>0x00000100</LFMASK>
<LFBITS>0x00000100</LFBITS>
<TEXT>Application reset, address $0</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x00000100</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>Boot loader reset</TEXT>
</OPT2>
</BOOTRESET>
<BOOTLOCK0>
<OPT1>
<LFMASK>0x0c000000</LFMASK>
<LFBITS>0x0c000000</LFBITS>
<TEXT>No restrictions for SPM or (E)LPM</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x0c000000</LFMASK>
<LFBITS>0x08000000</LFBITS>
<TEXT>No write to the Application section</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x0c000000</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>No write to Application section, No read from the Application section</TEXT>
</OPT3>
<OPT4>
<LFMASK>0x0c000000</LFMASK>
<LFBITS>0x04000000</LFBITS>
<TEXT>No read from the Application section</TEXT>
</OPT4>
</BOOTLOCK0>
<BOOTLOCK1>
<OPT1>
<LFMASK>0x30000000</LFMASK>
<LFBITS>0x30000000</LFBITS>
<TEXT>No restrictions for SPM or (E)LPM</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x30000000</LFMASK>
<LFBITS>0x20000000</LFBITS>
<TEXT>No write to the Boot Loader section</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x30000000</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>No write to Boot Loader section, No read from the Boot Loader section</TEXT>
</OPT3>
<OPT4>
<LFMASK>0x30000000</LFMASK>
<LFBITS>0x10000000</LFBITS>
<TEXT>No read from the Boot Loader section</TEXT>
</OPT4>
</BOOTLOCK1>
<WATCHDOG>
<TRUE>
<LFMASK>0x00001000</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>Watchdog always ON</TEXT>
</TRUE>
<FALSE>
<LFMASK>0x00001000</LFMASK>
<LFBITS>0x00001000</LFBITS>
<TEXT>Watchdog disabled</TEXT>
</FALSE>
</WATCHDOG>
<CLKDIV>
<VALUE>16</VALUE>
<TRUE>
<LFMASK>0x00000080</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>CLKDIV16 Fuse</TEXT>
</TRUE>
<FALSE>
<LFMASK>0x00000080</LFMASK>
<LFBITS>0x00000080</LFBITS>
<TEXT>CLKDIV16 Fuse </TEXT>
</FALSE>
</CLKDIV>
<CKOUT>
<TRUE>
<LFMASK>0x00000040</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>CKOUT Fuse</TEXT>
</TRUE>
<FALSE>
<LFMASK>0x00000040</LFMASK>
<LFBITS>0x00000040</LFBITS>
<TEXT>CKOUT Fuse</TEXT>
</FALSE>
</CKOUT>
<BOD>
<OPT1>
<LFMASK>0x000E0000</LFMASK>
<LFBITS>0x000E0000</LFBITS>
<TEXT>BOD disabled</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x000E0000</LFMASK>
<LFBITS>0x000C0000</LFBITS>
<TEXT>BOD enabled, 1.8 V</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x000E0000</LFMASK>
<LFBITS>0x000A0000</LFBITS>
<TEXT>BOD enabled, 2.7 V</TEXT>
</OPT3>
<OPT4>
<LFMASK>0x000E0000</LFMASK>
<LFBITS>0x00080000</LFBITS>
<TEXT>BOD enabled, 4.0 V</TEXT>
</OPT4>
</BOD>
</SETTINGS>
</ICE50>
</ICE_SETTINGS></AVRPART>
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